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ACS8520 Datasheet(PDF) 70 Page - Semtech Corporation

Part # ACS8520
Description  Synchronous Equipment Timing Source for Stratum 3/4E/4 and SMC Systems
PDF  150 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

ACS8520 Datasheet(HTML) 70 Page - Semtech Corporation

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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3.01/October 2003 © Semtech Corp.
Page 70
www.semtech.com
ACS8520 SETS
Address (hex):
10
Register Name sts_reference_sources
Input pairs (1 & 2)
Description
(RO except for test when R/W)
Reports any alarms active on
inputs.
Default Value
0110 0110
Bit 7Bit 6
Bit 5Bit 4
Bit 3Bit 2
Bit 1Bit 0
Address 10: Status of I2 Input
Address 11: Status of I4 Input
Address 12: Status of I6 Input
Address 13: Status of I8 Input
Address 14: Status of I10 Input
Address 15: Status of I12 Input
Address 16: Status of I14 Input
Address 10: Status of I1 Input
Address 11: Status of I3 Input
Address 12: Status of I5 Input
Address 13: Status of I7 Input
Address 14: Status of I9 Input
Address 15: Status of I11 Input
Address 16: Status of I13 Input
Bit No.
Description
Bit Value
Value Description
7 & 3
Out-of-band alarm (soft)
Soft out of band alarm bit for input. A “soft” alarm
will not invalidate an input.
0
1
No alarm.
Alarm armed. Alarm thresholds (range) set by
Reg. 49, or by Reg. 4A, Bits [7:4] if the input is
currently selected.
6 & 2
Out-of-band alarm (hard)
Hard out of band alarm bit for input. A “hard” alarm
will invalidate an input.
0
1
No alarm.
Alarm armed. Alarm thresholds set by Reg. 49 Bits
[3:0], or by Reg. 4A Bits [3:0] if the input is currently
selected.
5 & 1
No activity alarm
Alarm indication from the activity monitors.
0
1
No alarm.
Input has an active no activity alarm.
4 & 0
Phase lock alarm
If the DPLL can not indicate that it is phase locked
onto the current source within 100 seconds this
alarm will be raised.
0
1
No alarm.
Phase lock alarm.
Address (hex):
11
As Reg. 10, but for sts_reference_sources, Input pairs (3 & 4)
Address (hex):
12
As Reg. 10, but for sts_reference_sources, Input pairs (5 & 6)
Address (hex):
13
As Reg. 10, but for sts_reference_sources, Input pairs (7 & 8)
Address (hex):
14
As Reg. 10, but for sts_reference_sources, Input pairs (9 & 10)
Address (hex):
15
As Reg. 10, but for sts_reference_sources, Input pairs (11 & 12)
Address (hex):
16
As Reg. 10, but for sts_reference_sources, Input pairs (13 & 14)



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