PCD509X2 datasheet(9/16 Pages) PHILIPS

9 / 16 page

1998 Apr 27

Philips Semiconductors

Objective speciﬁcation

Low cost; low power DECT baseband

controllers (ABC-PRO)

PCD509x2/zuu/v family

Note

1. In the ‘State After Reset’ column the following symbols are used:

a) HIGH means active HIGH, for BUPxSW pin types this means weak pull-up

b) LOW means active LOW

c) ‘running’ means the clock signal is active

d) ‘off’ means the high-impedance state.

−

VDD(P0,P2) external access (80C51), active LOW

P3.7/RD

I/O

HIGH

VDD(P1,P3) 80C51 port pin/Read data, active LOW

P3.6/WR

I/O

HIGH

VDD(P1,P3) 80C51 port pin/Write data, active LOW

P3.5/T1

I/O

HIGH

VDD(P1,P3) 80C51 port pin/Timer 1 input

P3.4/T0

I/O

HIGH

VDD(P1,P3) 80C51 port pin/Timer 0 input

P3.3/INT1/IrDA

I/O

HIGH

VDD(P1,P3) 80C51 port pin/external interrupt 1/IrDA clock

P3.2/INT0

I/O

HIGH

VDD(P1,P3) 80C51 port pin/external interrupt 0

P3.1/TXD

I/O

HIGH

VDD(P1,P3) 80C51 port pin/UART transmit data

P3.0/RXD

I/O

HIGH

VDD(P1,P3) 80C51 port pin/UART receive data

VSSD

−−

−

negative supply voltage for digital core

VDDD

−−

−

positive supply voltage for digital core

VDD(P1,P3)

−−

−

positive supply voltage for periphery pins

P1.7/INT9/SDA

I/O

off

VDD(P1,P3) 80C51 port pin/external interrupt 9/I2C-bus data

P1.6/INT8/SCL

I/O

off

VDD(P1,P3) 80C51 port pin/external interrupt 8/I2C-bus clock

P1.5/INT7/FS1

I/O

HIGH

VDD(P1,P3) 80C51 port pin/external interrupt 7/SPI Frame Sync

P1.4/INT6/DCK

I/O

HIGH

VDD(P1,P3) 80C51 port pin/external interrupt 6/SPI Data Clock

P1.3/INT5/DO

I/O

HIGH

VDD(P1,P3) 80C51 port pin/external interrupt 5/SPI Data Out

P1.2/INT4/DI

I/O

HIGH

VDD(P1,P3) 80C51 port pin/external interrupt 4/SPI Data In

SYMBOL

I/O

STATE

AFTER

RESET(1)

SUPPLY

DOMAIN

DESCRIPTION

PCD509X2 Datasheet(PDF) 9 Page - NXP Semiconductors

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