CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

4

POST OFFICE BOX 655303

control pin settings

The CDCP1803 has three control pins (S0, S1, and S2) and an enable pin (EN) to select different output mode

settings.

RS0 = Open

EN

CDCP1803

S1

S0

RS1 = 0 Ω

REN = Open

Setting for Mode 20:

EN = 1

S2 = 1

S1 = 0

S0 = 1

RS2 = Open

S2

Figure 1. Control Pin Setting for Example

Table 1. Selection Mode Table

LVPECL

MODE

EN

S2

S1

S0

Y0

Y1

Y2

0

0

x

x

x

Off (high-z)

1

1

0

0

0

÷ 1

÷ 1

÷ 1

2

1

0

0

VDD/2

÷ 1

Off (high-z)

Off (high-z)

3

1

0

0

1

÷ 1

÷ 1

Off (high-z)

4

1

0

VDD/2

0

÷ 1

÷ 2

Off (high-z)

5

1

0

VDD/2

VDD/2

÷ 1

÷ 4

Off (high-z)

6

1

0

VDD/2

1

÷ 1

÷ 8

Off (high-z)

7

1

0

1

0

÷ 1

Off (high-z)

÷ 1

8

1

0

1

1

÷ 1

÷ 2

÷ 1

9

1

VDD/2

0

0

÷ 1

÷ 4

÷ 1

10

1

VDD/2

0

VDD/2

÷ 1

÷ 8

÷ 1

11

1

VDD/2

0

1

÷ 1

Off (high-z)

÷ 2

12

1

VDD/2

VDD/2

0

÷ 1

÷ 1

÷ 2

13

1

VDD/2

VDD/2

VDD/2

÷ 1

÷ 2

÷ 2

14

1

VDD/2

VDD/2

1

÷ 1

÷ 4

÷ 2

15

1

VDD/2

1

0

÷ 1

÷ 8

÷ 2

16

1

VDD/2

1

VDD/2

÷ 1

Off (high-z)

÷ 4

17

1

VDD/2

1

1

÷ 1

÷ 1

÷ 4

18

1

1

0

0

÷ 1

÷ 2

÷ 4

19

1

1

0

VDD/2

÷ 1

÷ 4

÷ 4

20

1

1

0

1

÷ 1

÷ 8

÷ 4

21

1

1

VDD/2

0

÷ 1

Off (high-z)

÷ 8

22

1

1

VDD/2

VDD/2

÷ 1

÷ 1

÷ 8