CDCP1803

1:3 LVPECL CLOCK BUFFER

WITH PROGRAMMABLE DIVIDER

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

1

POST OFFICE BOX 655303

Three LVPECL Differential Clock Outputs

LVPECL Outputs

Common-Mode Range

Single-Ended Input Signals

HSTL, CML, VML, SSTL-2, and

Single-Ended: LVTTL/LVCMOS

description

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential

clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCP1803 is specifically

designed for driving 50-

Ω transmission lines.

The CDCP1803 has three control pins, S0, S1, and S2, to select different output mode settings, see Table 1

for details. The CDCP1803 is characterized for operation from −40

°C to 85°C. For use in single-ended driver

applications, the CDCP1803 also provides a VBB output pin that can be directly connected to the unused input

as a common-mode voltage reference.

Copyright

 2004, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

MLF PACKAGE

(TOP VIEW)

1

2

3

4

6

5

18

17

13

14

15

16

EN

IN

VBB

S0

Y1

Vdd1

VddPECL

VddPECL

Vdd1

Y1

IN