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ADF5901WCCPZ Datasheet(PDF) 21 Page - Analog Devices

Part # ADF5901WCCPZ
Description  24 GHz to 24.25 GHz voltage controlled oscillator
PDF  27 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF5901WCCPZ Datasheet(HTML) 21 Page - Analog Devices

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ADF5901
Data Sheet
Rev. A | Page 20 of 26
12-Bit Integer Value (INT)
These 12 bits (Bits[DB28:DB17]) set the INT value, which
determines the integer part of the RF division factor. This INT
value is used in Equation 5. See the RF Synthesis: a Worked
Example section for more information. All integer values from
75 to 4095 are allowed.
12-Bit MSB Fractional Value (FRAC)
These 12 bits (Bits[DB16:DB5]), together with Bits[DB17:DB5]
(FRAC LSB word) in Register R6, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 12 bits are the most significant bits (MSB)
of the 25-bit FRAC value, and Bits[DB17:DB5] (FRAC LSB
word) in Register R6 are the least significant bits (LSB). See the
RF Synthesis: a Worked Example section for more information.
REGISTER 6
Control Bits
With Bits[C5:C1] set to 00110, Register R6 is programmed.
Figure 25 shows the input data format for programming
this register.
13-Bit LSB FRAC Value
These 13 bits (Bits[DB17:DB5]), together with Bits[DB16:DB5]
(FRAC MSB word) in Register R5, control what is loaded as the
FRAC value into the fractional interpolator. This FRAC value
partially determines the overall RF division factor. It is also used
in Equation 1. These 13 bits are the least significant bits (LSB)
of the 25-bit FRAC value, and Bits[DB14:DB3] (FRAC MSB
word) in Register R5 are the most significant bits (MSB). See
the RF Synthesis: a Worked Example section for more
information.
Figure 25. Register 6 (R6)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
C4(0) C3(1) C2(1) C1(0)
CONTROL
BITS
FRAC LSB WORD
C5(0)
F12
F11
..........
F1
F0
(FRAC)*
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
8188
1
1
..........
0
1
8189
1
1
..........
1
0
8190
1
1
.........
1
1
8191
1DBR = DOUBLE-BUFFERED REGISTER.
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER R5, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER R6. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 213.
FRAC LSB WORD
DBR1
RESERVED



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