MB95650L datasheet(83/105 Pages) CYPRESS

83 / 105 page

Document Number: 002-04696 Rev. *A

Page 83 of 105

MB95650L Series

(VCC = 3.0 V to 5.5 V, VSS = 0.0 V, TA = 40 °C to 85 °C)

(Continued)

Parameter

Symbol

name

Condition

Value*2

Unit

Remarks

Min

Max

Data setup time tSU;DAT

SCL0,

SCL1,

SDA0,

SDA1

R = 1.7 k

,

C = 50 pF*1

(-2

 nm/2) tMCLK  20 (-1  nm/2) tMCLK  20

Master mode

It is assumed that “L”

of SCL is not

extended. The

minimum value is

applied to the first bit

of continuous data.

Otherwise, the

maximum value is

applied.

Setup time

between

clearing

interrupt and

SCL rising

tSU;INT

SCL0,

SCL1

(nm/2) tMCLK  20

 nm/2) tMCLK  20

The minimum value

is applied to the

interrupt at the ninth

SCL

. The maximum

value is applied to

the interrupt at the

eighth SCL

.

SCL clock “L”

width

tLOW

SCL0,

SCL1

4 tMCLK  20

—

ns At reception

SCL clock “H”

width

tHIGH

SCL0,

SCL1

4 tMCLK  20

—

ns At reception

START

condition

detection

tHD;STA

SCL0,

SCL1,

SDA0,

SDA1

2 tMCLK  20

—

No START condition

is detected when

1tMCLK is used at

reception.

STOP condition

detection

tSU;STO

SCL0,

SCL1,

SDA0,

SDA1

2 tMCLK  20

—

No STOP condition is

detected when

1tMCLK is used at

reception.

RESTART

condition

detection

condition

tSU;STA

SCL0,

SCL1,

SDA0,

SDA1

2 tMCLK  20

—

No RESTART

condition is detected

when 1 tMCLK is used

at reception.

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