MB95650L datasheet(20/105 Pages) CYPRESS

20 / 105 page

Document Number: 002-04696 Rev. *A

Page 20 of 105

MB95650L Series

10. Block Diagram

Reset with LVD

Dual operation Flash with

security function

(36/20/12/8 Kbyte)

F2MC-8FX CPU

RAM (1024/512/256 bytes)

Oscillator

circuit

CR oscillator

Clock control

On-chip debug

Wild register

External interrupt

LIN-UART

8/16-bit composite timer ch. 0

I2C bus interface ch. 0

8/16-bit composite timer ch. 1

8/12-bit A/D converter

Port

PF2*1/RST*2

PF0/X0*2

PF1/X1*2

PG1/X0A*2

PG2/X1A*2

P02/INT02 to P07/INT07

(P02/SCK)

(P03/SOT)

(P04/SIN)

(P00/AN00 to P05*3/AN05)

(P12*1/DBG)

(P05/TO00)

(P06/TO01)

(P04/EC0), P12*1/EC0

UART/SIO ch. 0

P17/UI0

P62/UCK0

P16/UO0

(P62*3/TO10), P62*3/TO10

P63*3/TO11

P64/EC1

P14*1/SDA0

P15*1/SCL0

I2C bus interface ch. 1

(P16/SDA1)

(P17/SCL1)

Vcc

Vss

*1:

*2:

*3:

P12, P14, P15 and PF2 are N-ch open drain pins.

Software select

P05 to P07, P62 and P63 are high-current pins.

Note: Pins in parentheses indicate that those pins are shared among different peripheral functions.

MB95650L Datasheet(PDF) 20 Page - Cypress Semiconductor

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