ACT8870 datasheet(23/38 Pages) ACTIVE-SEMI

23 / 38 page

ACT8870QJ-T

REV 0 23-DEC-2016

Innovative PowerTM

ActiveSwitcherTM is a trademark of Active-Semi.

IC is powered on, but they are volatile and reset to the

factory defaults when power is recycled.

Softstart Time. The softstart time is the time it takes an

output to ramp from 0V to its programmed voltage. Each

output’s softstart time is configured via its I2C bit

SS_RAMP. Softstart times can be changed after the IC

is powered on, but they are volatile and reset to the

factory defaults when power is recycled.

Output Voltage. The output voltage is each regulator’s

desired voltage. Each buck’s output voltage is

programmed via its I2C bits Bx_VSET0 and Bx_VSET1.

The output regulates to Bx_VSET0 in ACTIVE mode.

They can be programmed to regulate to Bx_VSET1 in

DVS mode or SLEEP mode. Each output’s voltage can

be changed after the IC is powered on, but the new

setting is volatile and is reset to the factory defaults

when power is recycled. Output voltages can be

changed on the fly. If a large output voltage change is

required, it is best to make multiple smaller changes.

This prevents the IC from detecting an instantaneous

over or under voltage condition because the fault

threshold are immediately changed, but the output

takes time to respond.

Dynamic Voltage Scaling

On-the-fly dynamic voltage scaling (DVS) for the four

buck converters is available via the I2C interface. This

allows systems to save power by quickly adjusting the

microprocessor performance level when the workload

changes. Note that DVS is not a different operating

state. The IC operates in the ACTIVE state, but just

regulates the outputs to a different voltage. For fault free

operation, the user must ensure output load conditions

plus the current required to charge the output

capacitance during a DVS rising voltage condition does

not exceed the current limit setting of the regulator. As

with any power supply, changing an output voltage too

fast can require a current higher than the current limit

setting. The user must ensure that the voltage step,

slew rate, and load current conditions do not result in an

instantaneous loading that results in a current limit

condition.

Enter DVS by programming register 0x00h bit1

(DVS_EN) = 1 and then pulling the EXT_EN pin high.

Note that some CMI configurations may not require

DVS_EN = 1 and may use different input pins.

Fault Protection

The ACT8870 contains several levels of fault protection,

including the following:

Output Overvoltage

Output Undervoltage

Output Current Limit

Thermal Warning

Thermal Shutdown

There are three types of I2C register bits associated with

each fault condition: fault flag bits, fault bits, and mask

bits. The fault flag bits display the real-time fault status.

Their status is valid regardless of whether or not that

fault is masked. The mask bits either block or allow the

fault to affect the fault bit. Each potential fault condition

can be masked via I2C if desired. Any unmasked fault

condition results in the fault bit going high, which asserts

the IRQ pin. IRQ is typically active low. The IRQ pin

only de-asserts after the fault condition is no longer

present and the corresponding fault bit is read via I2C.

Note that masked faults can still be read in the fault flag

bit. Refer to Active-Semi Application Note describing the

programming ranges.

Output Under/Over Voltage

The ACT8870 monitors the output voltages for under

voltage and over voltage conditions. If one output enters

an UV/OV fault condition, the IC shuts down all outputs

for 100ms and restarts with the programmed power up

sequence. If an output is in current limit, it is possible

that its voltage can drop below the UV threshold which

also shuts down all outputs. If that behavior is not

desired, mask the appropriate fault bit. Each output still

provides its real-time UV/OV fault status via its fault flag,

even if the fault is masked. Masking an OV/UV fault just

prevents the fault from being reported via the IRQ pin.

A UV/OV fault condition pulls the nRESETx pins low.

Note that nRESETx pins are configurable via CMI

settings.

Output Current Limit

The ACT8870 incorporates a three level overcurrent

protection scheme for the buck converters and a single

level scheme for the LDOs. For the buck converters, the

overcurrent current threshold refers to the peak switch

current.

The first protection level is when a buck

converter’s peak switch current reaches 80% of the

Cycle-by-Cycle current limit threshold for greater than

16 switching cycles. Under this condition, the IC reports

the fault via the appropriate fault flag bit. If the fault is

unmasked, it asserts the IRQ pin. This may or may not

turn off that output or other outputs depending on the

specific CMI. The next level is when the current

increases to the Cycle-by-Cycle threshold. The buck

converter limits the peak switch current in each

switching cycle. This reduces the effective duty cycle

and causes the output voltage to drop, potentially

creating

undervoltage

condition.

When

the

overcurrent condition results in an UV condition, and UV

is not masked, the IC turns off all supplies off for 100ms

and restarts. The third level is when the peak switch

current reaches 120% of the Cycle-by-Cycle current

ACT8870 Datasheet(PDF) 23 Page - Active-Semi, Inc

ACT8870 Datasheet(HTML) 23 Page - Active-Semi, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL