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ZOPT2202AC5R Datasheet(PDF) 35 Page - Integrated Device Technology |
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ZOPT2202AC5R Datasheet(HTML) 35 Page - Integrated Device Technology |
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35 / 41 page ![]() ZOPT2202 Datasheet © 2016 Integrated Device Technology, Inc 35 September 21, 2016 3.10.15 LS_THRES_VAR Address 27HEX Default value 00HEX Register access RW Bit 7 6 5 4 3 2 1 0 27HEX 0 0 0 0 0 LS_THRES_VAR Bit[2:0] LS variance threshold Code Interrupt generated when 000BIN new DATA_x varies by 8 counts compared to previous result (default) 001BIN new DATA_x varies by 16 counts compared to previous result 010BIN new DATA_x varies by 32 counts compared to previous result 011BIN new DATA_x varies by 64 counts compared to previous result 100BIN new DATA_x varies by 128 counts compared to previous result 101BIN new DATA_x varies by 256 counts compared to previous result 110BIN new DATA_x varies by 512 counts compared to previous result 111BIN new DATA_x varies by 1024 counts compared to previous result 3.10.16 DEVICE_CONFIG Address 2FHEX Default value 00HEX Register access RW Bit 7 6 5 4 3 2 1 0 2FHEX 0 0 0 0 Reserved Reserved I²C Address Reserved Bit[1] I²C Address 0 (default) 7-bit format (no R/W bit consideration): 53HEX 8-bit format (with R/W bit consideration): A6 HEX / A7 HEX 1 7-bit format (no R/W bit consideration): 52HEX 8-bit format (with R/W bit consideration): A4 HEX / A5 HEX |
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