WM8750LEFLSLASHR datasheet(40/56 Pages) WOLFSON

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WM8750L

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PP Rev 1.77 May 2003

MASTER MODE ADCLRC AND DACLRC ENABLE

In Master mode, by default ADCLRC is disabled when the ADC is disabled and DACLRC is disabled

when the DAC is disabled. Register bit LRCM, register 24(18h) bit[2] changes the control so that the

ADCLRC and DACLRC are disabled only when ADC and DAC are disabled. This enables the user to

use e.g. ADCLRC for both ADC and DAC LRCLK and disable the ADC when DAC only operation is

required, (see Table 34).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24(18h)

Additional

Control (2)

LRCM

Selects disable mode for ADCLRC and

DACLRC

0 = ADCLRC disabled when ADC disabled,

DACLRC disabled when DAC disabled

1 = ADCLRC and DACLRC disabled only when

ADC and DAC are disabled

Table 34 ADCLRC/DACLRC Enable

CLOCK OUTPUT

By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0],

10 or 11 then ADCLRC pin is always an output even in slave mode or when TRI = ‘1’, (see Table 35).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R27(18h)

Additional

Control (3)

[8:7] ADCLRM

[1:0]

Configures ADCLRC pin

00 = ADCLRC is ADC word clock input (slave

mode) or ADCLRC output (master mode)

01 = ADCLRC pin is MCLK output

10 = ADCLRC pin is MCLK / 5.5 output

11 = ADCLRC pin is MCLK / 6 output

Table 35 ADCLRC Clock Output

CLOCKING AND SAMPLE RATES

The WM8750L supports a wide range of master clock frequencies on the MCLK pin, and can

generate many commonly used audio sample rates directly from the master clock. The ADC and

DAC do not need to run at the same sample rate; several different combinations are possible.

There are two clocking modes:

•

‘Normal’ mode supports master clocks of 128f

s, 192fs, 256fs, 384fs, and their multiples

(Note: f

s refers to the ADC or DAC sample rate, whichever is faster)

•

USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in

systems with a USB interface, and eliminates the need for an external PLL to generate

another clock frequency for the audio codec.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

CLKDIV2

Master Clock Divide by 2

1 = MCLK is divided by 2

0 = MCLK is not divided

5:1

SR [4:0]

0000

Sample Rate Control

R8 (08h)

Clocking and

Sample Rate

Control

USB

Clocking Mode Select

1 = USB Mode

0 = ‘Normal’ Mode

Table 36 Clocking and Sample Rate Control

The clocking of the WM8750L is controlled using the CLKDIV2, USB, and SR control bits. Setting the

CLKDIV2 bit divides MCLK by two internally. The USB bit selects between ‘Normal’ and USB mode.

Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination

of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their

accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change

proportionately.

Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their

target value by a very small amount. This is not audible, as the maximum deviation is only 0.27%

WM8750LEFL/R Datasheet(PDF) 40 Page - Wolfson Microelectronics plc

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