SSD50NBT datasheet(13/45 Pages) LSTD

13 / 45 page

SSD50NBT

Datasheet

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Feature

Description

Hardware Power

States

The SSD50NBT hardware has five top-level hardware power states managed by the RTC block.

State

Description

OFF

 CHIP_PWD_L pin assertion immediately brings the chip to the OFF state.

 Sleep clock is disabled.

 No state is preserved.

HOST_OFF

 WLAN is turned off. The Bluetooth clock is off but should also be powered

down through BT_PWD_L.

 Only the host interface is powered on. The rest of the chip is power gated

(off).

 The host instructs the SSD50NBT to transition to WAKEUP by writing a register

in the host interface domain.

 The embedded CPU and WLAN do not retain state (separate entry).

 For USB, this state can be bypassed by asserting FORCE_HOST_ON_L during

CHIP_PWD_L de-assertion.

SLEEP

 Only the sleep clock is operating.

 The crystal or oscillator is disabled.

 Any wakeup events force a transition from this state to the WAKEUP state.

 All internal states are maintained.

WAKEUP

 The system transitions from sleep states to ON.

 The high frequency clock is gated off as the crystal or oscillator is brought up

and the PLL is enabled.

 WAKEUP duration is programmable.

 The high speed clock is operational and sent to each block enabled by the

clock control register.

 Lower level clock gating is implemented at the block level, including the CPU,

which can be gated off using the WAITI instruction while the System is on.

 No CPU, host, and WLAN activities transition to sleep states. WLAN must be

initialized prior to Bluetooth initialization and use.

Sleep State

Management

Sleep state minimizes power consumption while saving system states. In sleep state, all high speed

clocks are gated off and the external reference clock source is powered off.

The system remains in sleep state until a WAKEUP event causes the system to enter WAKEUP state,

waits for the reference clock source to stabilize, and then un-gates all enabled clock trees. The

embedded CPU wakes up only when an interrupt arrives, which may have also generated the system

WAKEUP event.

SSD50NBT Datasheet(PDF) 13 Page - Laird Tech Smart Technology

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