LM9617 datasheet(10/37 Pages) NSC

10 / 37 page

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Functional Description

1.0

OVERVIEW

1.1

Light Capture and Conversion

The LM9617 contains a CMOS active pixel array consisting of

648 rows by 488 columns. This active region is surrounded by 8

columns and 8 rows of optically shielded (black) pixels as shown

in Figure.

8 columns, 8 rows

black pixels

8 columns, 8 rows

black pixels

648 columns, 488 rows

mono-chrome active pixels

Figure 7: CMOS APS region of the LM9617

At the beginning of a given integration time the on-board timing

and control circuit will reset every pixel in the array one row at a

time as shown in Figure 8. Note that all pixels in the same row

are simultaneously reset, but not all pixels in the array.

m n

CDS/Shift Register

Analog Data Out

Figure 8: CMOS APS Row and Column addressing scheme

At the end of the integration time, the timing and control circuit

will address each row and simultaneously transfer the integrated

value of the pixel to a correlated double sampling circuit and

then to a shift register as shown in Figure 8.

Once the correlated double sampled data has been loaded into

the shift register, the timing and control circuit will shift them out

one pixel at a time starting with column “a”.

The pixel data is then fed into an analog video amplifier, where a

user programmed gain is applied .

After gain adjustment the analog value of each pixel is con-

verted to a 12 bit digital data as shown in Figure 9.

12 Bit A/D

Video

AMP

Analog pixel values

Digital pixel data

0-15dB

Figure 9: Analog Signals In, Digital Data Out.

The digital pixel data is further processed to:

• remove defects due to bad pixels,

• compensate black level, before being framed and presented

on the digital output port. (see Figure 10).

Figure 10. Digital Pixel Processing.

1.2

Program and Control Interfaces

The programming, control and status monitoring of the LM9617

is achieved through a two wire I2C compatible serial bus. In

addition, a slave address pin is provided (see Figure 11).

Figure 11. Control Interface to the LM9617.

Additional control and status pins: snapshot and external event

synchronization are provided allowing the latency of the serial

control port to be bypassed during single frame capture. An

interrupt request pin is also available allowing complex snapshot

operations to be controlled via an external micro-processor (see

Figure 12).

Figure 12. Snapshot & External Event Trigger Signals

do[11:0]

pclk

hsync

vsync

2C Compatible

Serial I/F

sda

sclk

sadr

Timing

Generator

irq

snapshot

extsyn

LM9617 Datasheet(PDF) 10 Page - National Semiconductor (TI)

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