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LM9831CCVJDX Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LM9831CCVJDX Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 41 page ![]() 6 www.national.com Timing Diagrams Figure 1: DRAM Read and Write Column Addressn A0-A9 Row Addressn Row Addressn+1 RAS CAS RD Data D0-D15 tRD SETUP tRD HOLD WR Data D0-D15 tWR SETUP tWR HOLD 0 1234560 48MHz Internal Clock (tPERIOD = 20.83ns) Read Operation Write Operation RAS CAS 01234 560 48MHz Internal Clock (tPERIOD = 20.83ns) Figure 2: DRAM Refresh (CAS before RAS) |
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