Pin

Name

I/O

Typ

Description

11

DV+

P

+3V power supply for the digital circuits. Bypass each supply pin with 0.1 µF and

10 µF capacitors in parallel.

12

CLK

I

D

27 MHz clock input.

13

SHP

I

D

Correlated double sampler reset voltage clamp override. Programmable active-high or

active-low through serial interface. Connect to +3V digital supply when function not

being used (register values in default condition).

14

SHD

I

D

Correlated double sampler video signal voltage sample override. Programmable

active-high or active-low through serial interface. Connect to +3V digital supply when

function not being used (register values in default condition).

15

BOL

I

D

Active-high beginning of line switch input. Hold high during entire line of effective

pixels. Hold low during blanking period.

16

BLKCLP

I

D

Active-high black level clamp switch input. Pulse high during black pixels to eliminate

black pixel offset from video signal.

17

V

REFP

IO

A

Top of DAC reference ladder. Normally bypassed with a 0.1 µF capacitor. An external

DAC reference voltage may be applied to this pin.

18

V

REFN

IO

A

Bottom of DAC reference ladder. Normally bypassed with a 0.1 µF capacitor. An

external DAC reference voltage may be applied to this pin.

19

V

REFB

IO

A

Bottom of ADC reference ladder. Normally bypassed with a 0.1 µF capacitor. An

external ADC reference voltage may be applied to this pin.

20

CE

I

D

Active-low chip enable for the serial interface.

21

SCLK

I

D

Serial interface clock used to decode the serial input data.

22

SI DATA

I

D

Serial interface input port.

23

SO DATA

O

D

Serial interface output port.

24

DGND I/O

P

Digital output driver ground return.

25

DV+ I/O

P

+3V power supply for the digital output driver circuits. Bypass each supply pin with

0.1 µF and 10 µF capacitors in parallel.

26

D0

O

D

Digital output. Bit 0 of 9 (LSB) of the digital video output bus.

27

D1

O

D

Digital output. Bit 1 of 9 of the digital video output bus.

28

D2

O

D

Digital output. Bit 2 of 9 of the digital video output bus.

29

D3

O

D

Digital output. Bit 3 of 9 of the digital video output bus.

30

D4

O

D

Digital output. Bit 4 of 9 of the digital video output bus.

31

D5

O

D

Digital output. Bit 5 of 9 of the digital video output bus.

32

D6

O

D

Digital output. Bit 6 of 9 of the digital video output bus.

33

D7

O

D

Digital output. Bit 7 of 9 of the digital video output bus.

34

D8

O

D

Digital output. Bit 8 of 9 of the digital video output bus.

35

D9

O

D

Digital output. Bit 9 of 9 (MSB) of the digital video output bus.

36

DV+ I/O

P

+3V power supply for the digital output driver circuits. Bypass each supply pin with

0.1 µF and 10 µF capacitors in parallel.

37

DGND I/O

P

Digital output driver ground return.

38

DGND

P

Digital ground return.

39

DV+

P

+3V power supply for the digital circuits. Bypass each supply pin with 0.1 µF and 10

µF capacitors in parallel.

40

AV+

P

+3V power supply for the analog circuits. Bypass each supply pin with 0.1 µF and 10

µF capacitors in parallel.

41

AGND

P

Analog ground return.

42

V

REFT

IO

A

Top of ADC reference ladder. Normally bypassed with a 0.1 µF capacitor. An external

ADC reference voltage may be applied to this pin.

43

AV+

P

+3V power supply for the analog circuits. Bypass each supply pin with 0.1 µF and 10

µF capacitors in parallel.

44

AGND

P

Analog ground return.

45

AOUT−

O

A

Negative differential analog output from correlated double sampler or PGA (selectable

through the serial interface).

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