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LM98501CCVBH Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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LM98501CCVBH Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 24 page ![]() AC Electrical Characteristics The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, C L = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for T A = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol Parameter Conditions Min (Note 9) Typical (Note 8) Max (Note 9) Units f CLK Input Clock Frequency 1 27 30 MHz T CLK Input Clock Period 33 37 1000 ns t ch Clock High Time @ CLK max 15 ns t cl Clock Low Time @ CLK max 15 ns Clock Duty Cycle @ CLK max 45/55 min/max t rc,tfc Clock Input Rise and Fall Time 5 ns Pipeline Delay (Latency) 7 T CLK t VALID Data Valid Time 27 ns t OH Output Data Hold Time 9 13 19 ns t OD Output Delay Time 14 20 26 ns Full Channel Performance Specifications The following specifications apply for DV+ = AV+ = DV + I/O = +3.0V, C L = 10 pF, and fCLK = 27 MHz unless otherwise noted. Boldface limits apply for T A = TMIN to TMAX: all other limits TA = 25˚C (Note 7). Symbol Parameter Conditions Min (Note 9) Typical (Note 8) Max (Note 9) Units DNL Differential Non-Linearity −1.0 ±0.5 1.5 LSB INL Integral Non-Linearity +3.0/−1.5 LSB *SNR 0 dB Gain, 1.0V Input @ f CLK = 27 MHz 60 dB @ f CLK = 20 MHz 61 dB ENOB Effective Number of Bits @ f CLK = 27 MHz 7.5 Bits @ f CLK = 20 MHz 7.6 Bits THD Total Harmonic Distortion @ f CLK = 27 MHz −51 dB @ f CLK = 20 MHz −60 dB *20 log10 (VIN/RMS Output Noise) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is func- tional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed speci- fications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the voltage at any pin exceeds the power supplies (VIN < GND or VIN > AV+ or DV+), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with in input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJMAX) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJMAX, the junction-to-ambient thermal resistance (*JA), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJMAX –TA)/*JA. In the 48-pin LQFP, *JA is 69˚C/W, so PDMAX = 1,811 mW at 25˚C and 1,159 mW at the maximum operating ambient temperature of 70˚C. Note that the power dissipation of this device under normal operation will typically be about 180 mW. The values for maximum power dissipation listed above will be reached only when the LM98501 is operated in a severe fault condition. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through 0Ω. Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices. Note 7: The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be generated if the input goes above AV+ and below AGND. Note 8: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Note 9: Test limits are guaranteed to National’s AOQL (Averaging Outgoing Quality Level). DS101292-18 www.national.com 8 |
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