SC16C2552 datasheet(13/38 Pages) PHILIPS

13 / 38 page

Philips Semiconductors

SC16C2552

Dual UART with 16-byte transmit and receive FIFOs

Product data

Rev. 03 — 20 June 2003

13 of 38

9397 750 11636

7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

the TSR and UART via the THR, providing that the THR is empty. The THR empty

ﬂag in the LSR register will be set to a logic 1 when the transmitter is empty or when

data is transferred to the TSR. Note that a write operation can be performed when the

THR empty ﬂag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location

available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR) and

a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2552

and receive FIFO by reading the RHR register. The receive section provides a

mechanism to prevent false starts. On the falling edge of a start or false start bit, an

internal receiver counter starts counting clocks at the 16

× clock rate. After 7-1⁄2

clocks, the start bit time should be shifted to the center of the start bit. At this time the

start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in

this manner prevents the receiver from assembling a false character. Receiver status

codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready,

transmitter empty, line status and modem status registers. These interrupts would

normally be seen on the INTA, INTB output pins.

Table 7:

Interrupt Enable Register bits description

Bit

Symbol

Description

7-4

IER[7-4]

Not used; initialized to logic 0.

IER[3]

Modem Status Interrupt. This interrupt will be issued whenever

there is a modem status change as reﬂected in MSR[0-3].

Logic 0 = Disable the modem status register interrupt (normal

default condition).

Logic 1 = Enable the modem status register interrupt.

IER[2]

Receive Line Status interrupt. This interrupt will be issued

whenever a receive data error condition exists as reﬂected in

LSR[1-4].

Logic 0 = Disable the receiver line status interrupt (normal

default condition).

Logic 1 = Enable the receiver line status interrupt.

IER[1]

Transmit Holding Register interrupt. In the 16C450 mode, this

interrupt will be issued whenever the THR is empty, and is

associated with LSR[5]. In the FIFO modes, this interrupt will be

issued whenever the FIFO and THR are empty.

Logic 0 = Disable the Transmit Holding Register Empty (TXRDY)

interrupt (normal default condition).

Logic 1 = Enable the TXRDY (ISR level 3) interrupt.

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