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LMV111 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LMV111 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
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6 / 9 page ![]() Typical Performance Characteristics (Unless otherwise specified, V S = +5V, single supply, TA = 25˚C.) (Continued) Application Section The LMV111 integrates a rail-to-rail op amp and a V +/2 bias circuit into one ultra tiny package. With its small footprint and reduced component count for bias network, it enables the design of smaller portable electronic products, such as cellu- lar phones, pagers, PDAs, PCMCIA cards, etc. In addition, the integration solution minimizes printed circuit board stray capacitance, and reduces the complexity of circuit design. The core op amp of this family is National’s LMV321. 1.0 Supply Bypassing The application circuits in this datasheet do not show the power supply connections and the associated bypass ca- pacitors for simplification. When the circuits are built, it is al- ways required to have bypass capacitors. Ceramic disc ca- pacitors (0.1µF) or solid tantalum (1µF) with short leads, and located close to the IC are usually necessary to prevent in- terstage coupling through the power supply internal imped- ance. Inadequate bypassing will manifest itself by a low fre- quency oscillation or by high frequency instabilities. Sometimes, a 10µF (or larger) capacitor is used to absorb low frequency variations and a smaller 0.1µF disc is paral- leled across it to prevent any high frequency feedback through the power supply lines. 2.0 Input Voltage Range The input voltage should be within the supply rails. The ESD protection circuitry at the input of the device includes a diode between the input pin and the negative supply pin. Driving the input more than 0.6V (at 25˚C) beyond the negative sup- ply will turn on the diode and cause signal distortions. 3.0 Capacitive Load Tolerance The LMV111 can directly drive 200pF capacitive load with unity gain without oscillation. The unity-gain follower is the most sensitive configuration to capacitive loading. Direct ca- pacitive loading reduces the phase margin of amplifiers. The combination of the amplifier’s output impedance and the ca- pacitive load induces phase lag. This results in either an un- derdamped pulse or oscillation. To drive a heavier capacitive load, a resistive isolation can be used as shown in Figure 1. The isolation resistor R iso and the CL form a pole to increase stability by adding more phase margin to the overall system. The desired performance depends on the value of R iso.A 50 Ω to 100Ω isolation resistor is recommended for initial evaluation. The bigger the R iso resistor value, the more stable V OUT will be. Output Voltage Swing vs. Supply Voltage DS101262-22 DS101262-23 FIGURE 1. Resistive Isolation of a Heavy Capacitive Load www.national.com 6 |
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