TABLE 3. The F

RF1 R[19]

RF2 R[19]

RF1 R[20]

RF2 R[20]

F

(RF1 LD)

(RF2 LD)

(RF1 F

(RF2 F

Output State

0000

Disabled (Note 10)

0100

RF2 Lock Detect (Note 11)

1000

RF1 Lock Detect (Note 11)

1100

RF1/RF2 Lock Detect (Note 11)

X

0

0

1

RF2 Reference Divider Output

X

0

1

0

RF1 Reference Divider Output

X

1

0

1

RF2 Programmable Divider Output

X

1

1

0

RF1 Programmable Divider Output

0011

Fastlock (Note 12)

0111

RF2 Counter Reset (Note 13)

1011

RF1 Counter Reset (Note 13)

1111

RF1 and RF2 Counter Reset (Note 13)

X — don’t care condition

Note 11: Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output

is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.

occurs whenever the RF loop’s Icpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock).

Note 13: The RF2 counter reset mode resets RF2 PLL’s R and N counters and brings RF2 charge pump output to a TRI-STATE condition. The RF1 counter reset

mode resets RF1 PLL’s R and N counters and brings RF1 charge pump output to a TRI-STATE condition. The RF1 and RF2 counter reset mode resets all counters

and brings both charge pump output to a TRI-STATE condition. Upon removal of the Reset bits the N counter resumes counting in “close” alignment with the R

counter. (The maximum error is one prescaler cycle).

POWERDOWN OPERATION

Synchronous and asynchronous powerdown modes are

both available by microwire selection. Synchronously power-

down occurs if the respective loop’s R18 bit (Do TRI-STATE)

is LOW when its N20 bit (Pwdn) becomes HI. Asynchronous

powerdown occurs if the loop’s R18 bit is HI when its N20 bit

becomes HI.

In the synchronous powerdown mode, the powerdown func-

tion is gated by the charge pump to prevent unwanted fre-

quency jumps. Once the powerdown program bit N20 is

loaded, the part will go into powerdown mode when the

charge pump reaches a TRI-STATE condition.

In the asynchronous powerdown mode, the device powers

down immediately after the LE pin latches in a HI condition

on the powerdown bit N20.

Activation of either the IF or RF PLL powerdown conditions

in either synchronous or asynchronous modes forces the re-

spective loop’sR&N dividers to their load state condition

and debiasing of it’s respective Fin input to a high imped-

ance state. The oscillator circuitry function does not become

disabled until both IF and RF powerdown bits are activated.

The MICROWIRE control register remains active and ca-

pable of loading and latching data during all of the power-

down modes.

The device returns to an actively powered up condition in ei-

ther synchronous ar asynchronous modes immediately upon

LE latching LOW data into bit N20.

Powerdown Mode Select Table

R18

N20

Powerdown Status

0

0

PLL Active

1

0

PLL Active (Charge Pump Output

TRI-STATE)

0

1

Synchronous Powerdown Initiated

1

1

Asynchronous Powerdown Initiated

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