AD5170EVAL datasheet(5/24 Pages) AD

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AD5170

Rev. A | Page 5 of 24

TIMING CHARACTERISTICS — 2.5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD; VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.

Table 3.

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

I2C INTERFACE TIMING CHARACTERISTICS1 (Specifications apply to all parts)

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus Free Time between STOP and START

1.3

µs

tHD;STA Hold Time (Repeated START)

After this period, the first clock

pulse is generated.

0.6

µs

tLOW Low Period of SCL Clock

1.3

µs

tHIGH High Period of SCL Clock

0.6

µs

tSU;STA Setup Time for Repeated START Condition

0.6

µs

tHD;DAT Data Hold Time2

0.9

µs

tSU;DAT Data Setup Time

100

tF Fall Time of Both SDA and SCL Signals

300

tR Rise Time of Both SDA and SCL Signals

300

tSU;STO Setup Time for STOP Condition

t10

0.6

µs

1 See timing diagrams for locations of measured values.

2 The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.

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