AN2521

Functional check

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output load level. This pin is intended to drive the base of a PNP transistor in systems

including a PFC pre-regulator, to stop the PFC controller at light load by cutting its supply.

Pin #14 (PFC_STOP), while normally low, opens if the voltage on the COMP pin is lower

than 2.2 V, and returns low when the voltage on the COMP pin exceeds 2.7 V. Whenever the

IC is shut down, either latched (DIS > 2.2 V, ISEN > 1.5 V) or not latched (UVLO, SKIPADJ <

powered with a good margin with respect to the L6668 turn-off threshold (9.4 V), avoiding

any spurious turn-off possibilities that could affect the output voltage stability.

In Table 3, the power consumption from the mains during no-load operation is shown. As

can be observed, thanks to the L6668 standby functionality the input power constantly

remains well below 300 mW. Therefore, all mandatory or voluntary regulations currently

applicable or that will become effective in the near future can be respected using this

chipset.

In Figure 20 and Figure 21, the transitions from full load to no-load and vice-versa at

maximum input voltage have been checked. The maximum input voltage has been chosen

for the above illustrations because it is the most critical input voltage for transition. In fact, at

restart cycles of the controller. Additionally, there is a wider range variation for the input

Table 3.

Input power at no-load vs. mains voltage

Vin [Vrms]

Input power [W]

90

0.126

115

1.

Compliant to CEC, EU-COC, Energy Star

230

265

0.282

Figure 20.

EVAL6668-75 W transition full load-

to-no load at 265 V, 50 Hz

Figure 21.

EVAL6668-75 W transition no load-

to-full load at 265 V, 50 Hz

CH1: Q2 drain voltage

CH2: L6668 SOFT START - pin #11

CH3: output voltage

CH1: Q2 drain voltage

CH2: L6668 SOFT START - pin #11

CH3: output voltage