PC87200 datasheet(11/33 Pages) NSC

11 / 33 page

5.0 Pin Descriptions (Continued)

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DEVSEL#

I/O

t/s

PCI Device Select

DEVSEL# is asserted by a PCI slave, to indicate to a PCI master and subtractive

decoder that it is the target of the current transaction.

As an input, DEVSEL# indicates a PCI slave has responded to the current ad-

dress.

As an output, DEVSEL# is asserted one cycle after the assertion of FRAME#

and remains asserted to the end of a transaction as the result of a positive de-

code. DEVSEL# is asserted four cycles after the assertion of FRAME# if the

PC87200 is selected as the result of a subtractive decode. The subtractive de-

code sample point can be configured in F0 Index 41h[2:1]. These cycles are

passed to the ISA bus.

PAR

I/O

t/s

PCI Parity

PAR is the parity signal driven to maintain even parity across AD[31:0] and

C/BE[3:0]#.

The PC87200 drives PAR one clock after the address phase and one clock after

each completed data phase of write transactions as a PCI master. It also drives

PAR one clock after each completed data phase of read transactions as a PCI

slave.

SERR#

PCI System Error

SERR# is pulsed by a PCI device to indicate an address parity error.

Signal Name

Pin No.

Type

Description

PC87200 Datasheet(PDF) 11 Page - National Semiconductor (TI)