PC87317 datasheet(7/272 Pages) NSC

7 / 272 page

Table of Contents

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4.4.1

The ONCTL Flip-Flop and Signal ................................................................................ 62

4.4.2

Entering Power States ................................................................................................. 65

4.4.3

System Power-Up and Power-Off Activation Event Description .................................. 67

4.5

APC REGISTERS ...................................................................................................................... 69

4.5.1

APC Control Register 1 (APCR1) ................................................................................ 70

4.5.2

APC Control Register 2 (APCR2) ................................................................................ 70

4.5.3

APC Status Register (APSR) ...................................................................................... 71

4.5.4

Wake up Day of Week Register (WDWR) ................................................................... 71

4.5.5

Wake up Date of Month Register (WDMR) ................................................................. 72

4.5.6

Wake up Month Register (WMR) ................................................................................. 72

4.5.7

Wake up Year Register (WYR) .................................................................................... 72

4.5.8

RAM Lock Register (RLR) ........................................................................................... 72

4.5.9

Wake up Century Register (WCR) .............................................................................. 73

4.5.10

APC Control Register 3 (APCR3) ................................................................................ 73

4.5.11

APC Control Register 4 (APCR4), Bank 2, Index 4Ah ................................................ 74

4.5.12

APC Control Register 5 (APCR5) ................................................................................ 75

4.5.13

APC Control Register 6 (APCR6) ................................................................................ 75

4.5.14

APC Control Register 7 (APCR7) ................................................................................ 76

4.5.15

APC Status Register 1 (APSR1) ................................................................................. 77

4.5.16

Day-of-Month Alarm Address Register (DADDR) ........................................................ 77

4.5.17

Month Alarm Address Register (MADDR) ................................................................... 77

4.5.18

Century Address Register (CADDR) ........................................................................... 77

4.6

ACPI FIXED REGISTERS ......................................................................................................... 78

4.6.1

Power Management 1 Status Low Byte Register (PM1_STS_LOW) .......................... 78

4.6.2

Power Management 1 Status High Byte Register (PM1_STS_HIGH) ........................ 78

4.6.3

Power Management 1 Enable Low Byte Register (PM1_EN_LOW) ........................... 79

4.6.4

Power Management 1 Enable High Byte Register (PM1_EN_HIGH) ......................... 79

4.6.5

Power Management 1 Control Low Byte Register (PM1_CNT_LOW) ........................ 80

4.6.6

Power Management 1 Control High Byte Register (PM1_CNT_HIGH) ....................... 80

4.6.7

Power Management Timer Low Byte Register (PM1_TMR_LOW) ............................. 80

4.6.8

Power Management Timer Middle Byte Register (PM1_TMR_MID) ........................... 81

4.6.9

Power Management Timer High Byte Register (PM1_TMR_HIGH) ............................ 81

4.6.10

Power Management Timer Extended Byte Register (PM1_TMR_EXT) ...................... 81

4.7

GENERAL PURPOSE EVENT REGISTERS ............................................................................ 81

4.7.1

General Purpose 1 Status Register (GP1_STS0) ....................................................... 81

4.7.2

General Purpose 1 Status 1 Register (GP1_STS1), Offset 01h .................................. 82

4.7.3

General Purpose 1 Status 2 Register (GP1_STS2), Offset 02h .................................. 82

4.7.4

General Purpose 1 Status 3 Register (GP1_STS3), Offset 03h .................................. 82

4.7.5

General Purpose 1 Enable 0 Register (GP1_EN0) ..................................................... 82

4.7.6

General Purpose 1 Enable 1 Register (GP1_EN1), Offset 05h ................................... 83

4.7.7

General Purpose 1 Enable 2 Register (GP1_EN2), Offset 06hr ................................. 83

4.7.8

General Purpose 1 Enable 3 Register (GP1_EN3), Offset 07h ................................... 83

4.7.9

General Purpose 2 Enable 0 Register (GP2_EN0) ..................................................... 83

4.7.10

Bit 3 - IRRX2 Enable (IRRX2_E) ................................................................................. 83

4.7.11

SMI Command Register (SMI_CMD), Offset 0Ch ....................................................... 83

4.8

RTC AND APC REGISTER BITMAPS ...................................................................................... 84

4.8.1

RTC Register Bitmaps ................................................................................................. 84

PC87317 Datasheet(PDF) 7 Page - National Semiconductor (TI)

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