PC87351 datasheet(59/86 Pages) NSC

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4.0 General-Purpose Input/Output (GPIO) Port (Continued)

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4.3

INTERRUPT ASSERTION AND HANDLING

The enhanced GPIO port supports interrupt assertion and handling. This functionality is based on three configuration bits

and a bit slice of runtime registers GPIEN and GPST. The configuration and operation of the interrupt capability is shown in

Figure 4-3.

Figure 4-3. Interrupt Assertion

4.3.1

Interrupt Configuration

Each pin in the GPIO port is a potential interrupt source. The interrupt generator can trigger an interrupt upon predetermined be-

havior of the source pin. The GPIO Configuration Register determines the interrupt generation trigger type for the interrupt assertion.

IRQ Polarity

Two trigger types of interrupt assertion are supported: edge and level. An edge interrupt may be asserted upon a source pin

transition either from high to low or low to high. A level interrupt may be asserted when the source pin is in active level. The

trigger type is determined by IRQ Type (bit 4 of the GPIO Configuration Register). The direction of the transition (for edge)

or the polarity of the active level (for level) is determined by IRQ Polarity (bit 5 of the GPIO Configuration Register).

IRQ Debounce Enable

The input signal for the interrupt can be debounced for about 15 msec. The signal state should be transferred only after a

debouncing period during which the signal has no transitions, to ensure that the signal is stable. The debouncer adds 15

msec delay to both assertion and de-assertion level interrupts, and to the assertion of edge interrupts. When working with a

level interrupt, it is recommended to disable the debounce if the delay in the interrupt de-assertion is not acceptable.

The debounce is controlled by IRQ Debounce Enable (bit 6 of the GPIO Configuration Register).

4.3.2

Interrupt Assertion

The interrupt assertion for each GPIO pin is controlled by the corresponding bit in the GPIEN Register. Interrupt assertion

by a GPIO pin is enabled if the corresponding bit of this register is set to 1.

The GPST Register is a general-purpose edge detector which may be used to reflect the interrupt source pending status for

edge-triggered interrupts.

The term

active edge refers to a change in a GPIO pin level that matches the IRQ Polarity bit (1 for rising edge and 0 for

falling edge).

Active level refers to the GPIO pin level that matches the IRQ Polarity bit (1 for high level and 0 for low level).

The corresponding bit of the GPST Register is set by hardware whenever an active edge is detected, regardless of any other

bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.

Interrupt

Enable

IRQ Polarity

Interrupt

Requests

GPIO Pins

Input

Debouncer

Interrupt

Request

Internal

Bus

Level =1

R/W 1 to Clear

Status

Rising Edge or

Rising

Edge

Detector

from other

High Level =1

GPIO Conﬁguration Register

IRQ Type

IRQ

Debounce

Enable

R/W

Bit 6

Bit 5

Bit 4

PC87351 Datasheet(PDF) 59 Page - National Semiconductor (TI)

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