PC87364 datasheet(41/180 Pages) NSC

41 / 180 page

2.0 Device Architecture and Configuration (Continued)

www.national.com

When VSB is first applied, the PSC state machine is initialized to Power Fail state. In this state, the mechanism waits for the

PC87364 to be initialized according to strap options. Then the PSC enters Check Resume Mode state. In this state, the PSC

checks if Resume to Last PSON state is enabled.

If Resume to Last PSON is enabled, PSON immediately resumes the state it was in when VSB was lost. To enable this mech-

anism, set bit 2 of the SIOCFD register to 1, and program the ACPI controller to resume OFF state (SLPS3 = 0) after power

fail recovery to allow the PSC to operate properly. If the last state of PSON was OFF, assuming that the ACPI controller also

resumed OFF state, PSON is set to inactive and the PSC enters OFF state. If the last state was ON, under the same as-

sumption, the ACPI controller must be notified to change its state to ON. This is done by pulsing the PWBTOUT output. This

synchronization pulse is generated when the PSC is in Synchronize ACPI state.

If Resume Last PSON State is disabled, the PSC enters either ON or OFF state according to the value of the SLPS3 input,

as follows:

If SLPS3 is low (active, state OFF), the PSC enters OFF state.

If SLPS3 is high (inactive, state ON), the PSC enters ON state.

Since SLPS3 reflects the state of the ACPI controller, the PSC actually resumes the current state of the ACPI controller.

After entering either ON or OFF states, PSC moves between these two states on the following conditions:

A falling edge on PWBTOUT (generated internally) changes the state from ON to OFF or vice versa.

A Software Power Supply Off command, writing 1 to Power Supply Off (bit 1) of the SIOCFD register, changes the

state from ON to OFF.

Since many wake-up events can activate the PWBTOUT signal, these events can actually cause the PSC to change its state

from OFF to ON, thus activating the PSON output.

As in ACPI mode, the Crowbar protection mechanism is also active in Legacy mode. However, in this mode, when a Crowbar

condition is detected, the PSC returns to OFF state, thus inactivating the PSON output. Also, to synchronize the APCI con-

troller, the PWBTOUT is pulsed to bring it to the correct state.

Table 13 summarizes the bit states that affect PSON VSB power-up default state.

Table 13. PSON VSB Power-Up Default State

Crowbar Condition

A Crowbar condition is a situation in which the signal that directly controls the system’s power supply is active for a certain

duration of time, without a power supply response. To prevent this deadlock and enable reactivation of the power supply, a

special crowbar mechanism is included in the PSC logic.

Once the PSON is activated, assuming the power supply is off, a timer in the PSC logic starts counting. If this timer reaches

its terminal count before the power supply becomes active, the PSC detects a Crowbar condition. In this case, PSON is

deactivated and the PSC makes sure that the ACPI state of the system is changed to OFF.

The time that causes a Crowbar condition is defined as the Crowbar Timeout. The Crowbar Timeout of the PSC can be pro-

grammed to values between 0.5-2.25 seconds. This Timeout value is set by writing the appropriate value to bit 4-3 of the

SIOCFD register. For further details, refer to the description of this register in Section 2.8.12.

Resume Last

PSON State

(SIOCFD, Bit 2)

Last PSON

State

PSON VSB Power-Up

Default

Same as SLPS3 state

PC87364 Datasheet(PDF) 41 Page - National Semiconductor (TI)

PC87364 Datasheet(HTML) 41 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL