PC87364 datasheet(23/180 Pages) NSC

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1.0 Signal/Pin Connection and Description (Continued)

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1.4.8

Keyboard and Mouse Controller (KBC)

1.4.9

Parallel Port

Signal

Pin/s

I/O Buffer Type Power Well

Description

GA20

I/O

INT/OD2

VDD

Gate A20. KBC gate A20 (P21) output.

KBCLK

111

I/O

INTS/OD14

VDD,VSB

Keyboard Clock. Transfers the keyboard clock between the

SuperI/O chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P26 signal, and is

connected internally to the T0 signal of the KBC. External pull-up

resistor to 5V is required (for PS/2 compliance). The pin is

monitored for wake-up event detection. To enable the activity

during power off, it must be pulled up to Keyboard and Mouse

standby voltage.

KBDAT

112

I/O

INTS/OD14

VDD,VSB

Keyboard Data. Transfers the keyboard data between the SuperI/O

chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P27 signal, and is

connected internally to KBC P10. External pull-up resistor to 5V is

required (for PS/2 compliance). The pin is monitored for wake-up

event detection. To enable the activity during power off, it must be

pulled up to Keyboard and Mouse standby voltage.

KBRST

I/O

INT/OD2

VDD

KBD Reset. Keyboard Reset (P20) output.

MCLK

113

I/O

INTS/OD14

VDD,VSB

Mouse Clock. Transfers the mouse clock between the SuperI/O

chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P23 signal, and is

connected internally to KBC T1. External pull-up resistor to 5V is

required (for PS/2 compliance). The pin is monitored for wake-up

event detection. To enable the activity during power off, it must be

pulled up to Keyboard and Mouse standby voltage.

MDAT

114

I/O

INTS/OD14

VDD,VSB

Mouse Data. Transfers the mouse data between the SuperI/O

chip and the external keyboard using the PS/2 protocol.

This pin is driven by the internal, inverted KBC P22 signal, and is

connected internally to KBC P11. External pull-up resistor to 5V is

required (for PS/2 compliance). The pin is monitored for wake-up

event detection. To enable the activity during power off, it must be

pulled up to Keyboard and Mouse standby voltage.

P12, P16,

P17

6,127,

I/O

INT/OD2

VDD

I/O Port. KBC open-drain signal for general-purpose input and

output, controlled by KBC ﬁrmware.

Signal

Pin/s

I/O

Buffer Type Power Well

Description

ACK

INT

VDD

Acknowledge. Pulsed low by the printer to indicate that it has

received data from the Parallel Port.

AFD_DSTRB 93

OD14,O14/14

VDD

AFD - Automatic Feed. When low, instructs the printer to

automatically feed a line after printing each line. This pin is in

TRI-STATE after a 0 is loaded into the corresponding control

Ω pull-up resistor should be

attached to this pin.

DSTRB - Data Strobe (EPP). Active low, used in EPP mode

to denote a data cycle. When the cycle is aborted, DSTRB

becomes inactive (high).

BUSY_WAIT 78

INT

VDD

Busy. Set high by the printer when it cannot accept another

character.

Wait. In EPP mode, the Parallel Port device uses this active

low signal to extend its access cycle.

ERR

INT

VDD

Error. Set active low by the printer when it detects an error.

PC87364 Datasheet(PDF) 23 Page - National Semiconductor (TI)

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