TNETV2501INPGF datasheet(160/197 Pages) TI1

160 / 197 page

Electrical Specifications

160

December 2002 − Revised November 2008

SPRS206K

5.9

Reset Timings

Table 5−17 and Table 5−18 assume testing over recommended operating conditions (see Figure 5−22).

Table 5−17. Reset Timing Requirements †

NO.

MIN

MAX

UNIT

tw(RSL)

Pulse width, RESET low

2P + 5

† P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.

Table 5−18. Reset Switching Characteristics †

NO.

PARAMETER

MIN

MAX

UNIT

td(RSL-EMIFHZ)

Delay time, RESET low to EMIF group high impedance‡

td(RSH-EMIFV)

Delay time, RESET high to EMIF group valid‡

GPIO4 = 0 (CLKMOD = 0)

41115P + 21

td(RSH-EMIFV)

Delay time, RESET high to EMIF group valid‡

GPIO4 = 1 (CLKMOD = 1)

148P + 22

td(RSL-HIGHIV)

Delay time, RESET low to high group invalid§

td(RSH-HIGHV)

Delay time, RESET high to high group valid§

GPIO4 = 0 (CLKMOD = 0)

41044P + 17

td(RSH-HIGHV)

Delay time, RESET high to high group valid§

GPIO4 = 1 (CLKMOD = 1)

77P + 18

td(RSL-ZHZ)

Delay time, RESET low to Z group high impedance¶

td(RSH-ZV)

Delay time, RESET high to Z group invalid¶

GPIO4 = 0 (CLKMOD = 0)

41044P + 18

td(RSH-ZV)

Delay time, RESET high to Z group invalid¶

GPIO4 = 1 (CLKMOD = 1)

77P + 19

td(RSL-IOIM)

Delay time, RESET low to Input/Output group switch to input mode#

td(RSL-TGLD)

Delay time, RESET low to Toggle group switch to default toggle frequency||

11 + 14P

† P = the period of the clock on the X2/CLKIN pin in ns. For example, when using 20 MHz as the input clock, use P = 50 ns.

‡ EMIF group: EMIF.A[21:2], EMIF.ARE/SADS/SDCAS/SRE, EMIF.AOE/SOE/SDRAS, EMIF.AWE/SWE/SDWE, EMIF.ARDY, EMIF.CE0,

EMIF.CE1, EMIF.CE2, EMIF.CE3, EMIF.BE0, EMIF.BE1, EMIF.BE2, EMIF.BE3, EMIF.SDCKE, EMIF.SOE3, EMIF.HOLD, EMIF.HOLDA,

ECLKOUT1.

EMIF.ARDY and EMIF.HOLDA do not go to a high-impedance state during reset since they are input-only signals; they are included here simply

for completeness.

§ High group: IACK, XF, SCL (assumes external pullup on pin), SDA (assumes external pullup on pin), UART.TX, TDO.

¶ Z group: HRDY, HINT, DX1, DX0

# Input/Output group: PGPIO[45:0], HPI.HD[7:0], EMIF.D[31:0], HPI.HAS, HPI.HBIL, HCNTL1, HCNTL0, HCS, HR/W, HDS1, HDS2,

NMI/WDTOUT, GPIO[7:0], TIM0, TIM1, CLKR0, CLKX0, FSR0, FSX0, CLKR1, CLKX1, FSR1, FSX1, EMU0, EMU1/OFF. Signals in this group

switch to input mode with reset.

|| Toggle group: ECLKOUT2, CLKOUT. Pins in this group toggle with a default frequency during reset.

TNETV2501INPGF Datasheet(PDF) 160 Page - Texas Instruments

TNETV2501INPGF Datasheet(HTML) 160 Page - Texas Instruments

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