TNETV2501INPGF datasheet(99/197 Pages) TI1

99 / 197 page

Functional Overview

December 2002 − Revised November 2008

SPRS206K

3.11.2.5

Parallel GPIO Direction Register 1 (PGPIODIR1)

IO31DIR

IO30DIR

IO29DIR

IO28DIR

IO27DIR

IO26DIR

IO25DIR

IO24DIR

R/W, 0

IO23DIR

IO22DIR

IO21DIR

IO20DIR

IO19DIR

IO18DIR

IO17DIR

IO16DIR

R/W, 0

LEGEND: R = Read, W = Write, n = value at reset

Figure 3−38. Parallel GPIO Direction Register 1 Layout (0x4404)

Table 3−40. Parallel GPIO Direction Register 1 Bit Field Description†

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

IOxDIR

15−0

R/W

0000000000000000

Data direction bits specify if corresponding bits in the data

registers specify an output value or an input value. See

Table 3−35, TMS320VC5501 PGPIO Cross-Reference to deter-

mine which device pins correspond to the PGPIO pins.

IOxDIR = 0:

Corresponding bit in the data register specifies

the value read on the PGPIOx pin (input). When

IOxDIR = 0, IOxEN must also be cleared to 0.

IOxDIR = 1:

Corresponding bit in the data register specifies

the value driven on the PGPIOx pin (output).

When IOxDIR = 1, IOxEN must also be set to 1.

† x = value from 16 to 31

TNETV2501INPGF Datasheet(PDF) 99 Page - Texas Instruments

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