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TNETV2501INPGF Datasheet(PDF) 107 Page - Texas Instruments

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Part # TNETV2501INPGF
Description  Fixed-Point Digital Signal Processor
PDF  197 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV2501INPGF Datasheet(HTML) 107 Page - Texas Instruments

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Functional Overview
107
December 2002 − Revised November 2008
SPRS206K
3.13.1.1 XPORT Configuration Register (XCR)
The XPORT Configuration Register bit layout is shown in Figure 3−44 and the bits are described in
Table 3−48.
15
14
8
INTERREN
Reserved
R/W, 1
R, 0000000
7
0
Reserved
R, 00000000
LEGEND: R = Read, W = Write, n = value at reset
Figure 3−44. XPORT Configuration Register Layout (0x0100)
Table 3−48. XPORT Configuration Register Bit Field Description
BIT NAME
BIT NO.
ACCESS
RESET VALUE
DESCRIPTION
INTERREN
15
R/W
1
INTERREN bit
INTERREN = 0:
The XPORT will not generate a bus error for
invalid accesses to registers listed in Table 3−47.
Note that any invalid accesses to these registers
will hang the pipeline.
INTERREN = 1:
The XPORT will generate a bus error for invalid
accesses to registers listed in Table 3−47.† Note
that when a bus error occurs, any data returned
by the read instruction will not be valid.
Reserved
14−0
R
000000000000000
Reserved
† This feature will not work if the XPORT is placed in idle through the ICR. However, a bus error will be generated if the XPORT is placed in idle
without the CPU being in idle.



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