SCAN18541T datasheet(4/14 Pages) NSC

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Description of Boundary-Scan Circuitry

The scan cells used in the BOUNDARY-SCAN register are

one of the following two types depending upon their location.

Scan cell TYPE1 is intended to solely observe system data,

while TYPE2 has the additional ability to control system

data. (See IEEE Standard 1149.1

Figure10–11 for a further

description of scan cell TYPE1 and

Figure 10–12 for a fur-

ther description of scan cell TYPE2.)

Scan cell TYPE1 is located on each system input pin while

scan cell TYPE2 is located at each system output pin as well

as at each of the two internal active-high output enable sig-

nals. AOE controls the activity of the A-outputs while BOE

controls the activity of the B-outputs. Each will activate their

respective outputs by loading a logic high.

The BYPASS register is a single bit shift register stage iden-

tical to scan cell TYPE1. It captures a fixed logic low.

The INSTRUCTION register is an 8-bit register which cap-

tures the default value of 10000001. The two least significant

bits of this captured value (01) are required by IEEE Std

1149.1. The upper six bits are unique to the SCAN18541T

device. SCAN CMOS Test Access Logic devices do not in-

clude the IEEE 1149.1 optional identification register. There-

fore, this unique captured value can be used as a “pseudo

ID” code to confirm that the correct device is placed in the

appropriate location in the boundary scan chain.

MSB→LSB

Instruction Code

Instruction

00000000

EXTEST

10000001

SAMPLE/PRELOAD

10000010

CLAMP

00000011

HIGH-Z

All Others

BYPASS

Bypass Register Scan Chain Definition

Logic 0

DS100324-9

Instruction Register Scan Chain Definition

DS100324-10

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