ST72344S2 datasheet(105/247 Pages) STMICROELECTRONICS

105 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

105/247

Figure 54.

Pulse width modulation mode timing example

OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1

Pulse-width modulation mode

Pulse-width modulation (PWM) mode enables the generation of a signal with a frequency

and pulse length determined by the value of the OC1R and OC2R registers.

Pulse-width modulation mode uses the complete Output Compare 1 function plus the OC2R

In PWM mode, double buffering is implemented on the output compare registers. Any new

values written in the OC1R and OC2R registers are loaded in their respective shadow

registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the

PWM output pin (OCMP1). The shadow registers contain the reference values for

comparison in PWM “double buffering” mode.

Note:

There is a locking mechanism for transferring the OCiR value to the buffer. After a write to

the OCiHR register, the transfer of the new compare value to the buffer is inhibited until

OCiLR is also written.

Unlike in Output Compare mode, the compare function is always enabled in PWM mode.

Procedure:

To use pulse-width modulation mode:

Load the OC2R register with the value corresponding to the period of the signal using

the formula in the opposite column.

Load the OC1R register with the value corresponding to the period of the pulse if

(OLVL1=0 and OLVL2=1) using the formula in the opposite column.

Select the following in the CR1 register:

–

Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with OC1R register.

–

Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a

successful comparison with OC2R register.

Select the following in the CR2 register:

–

Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.

–

Set the PWM bit.

–

Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).

COUNTER 34E2

34E2

FFFC

OLVL2

OLVL1

OCMP1

compare2

compare1

compare2

FFFC FFFD FFFE

2ED0

2ED1 2ED2

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