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ST72325AR7-Auto Datasheet(PDF) 117 Page - STMicroelectronics

Part # ST72325AR7-Auto
Description  SCI asynchronous serial interface
PDF  243 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72325AR7-Auto Datasheet(HTML) 117 Page - STMicroelectronics

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Obsolete
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Product(s)
ST72325xxx-Auto
16-bit timer
Doc ID 13770 Rev 3
117/243
13.7
16-bit timer registers
Each timer is associated with 3 control and status registers, and with 6 pairs of data
registers (16-bit values) relating to the 2 input captures, the 2 output compares, the counter
and the alternate counter.
13.7.1
Control register 1 (CR1)
One Pulse mode
No
Not
recommended(1)
No
Partially(2)
PWM mode
Not
recommended(3)
No
1.
See Note 4 in Section 13.3.6 One Pulse mode
2.
See Note 5 in Section 13.3.6 One Pulse mode
3.
See Note 4 in Section 13.3.7 Pulse width modulation mode
Table 59.
Timer modes
Modes
Timer resources
Input
Capture 1
Input
Capture 2
Output
Compare 1
Output
Compare 2
CR1
Reset value: 0000 0000 (00h)
76
543
21
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
RW
RW
RW
RW
RW
RW
RW
RW
Table 60.
CR1 register description
Bit
Name
Function
7ICIE
Input Capture Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is
set.
6OCIE
Output Compare Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register
is set.
5
TOIE
Timer Overflow Interrupt Enable
0: Interrupt is inhibited
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
4FOLV2
Forced Output Compare 2
This bit is set and cleared by software.
0: No effect on the OCMP2 pin
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and
even if there is no successful comparison



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