ST72325AR7-Auto datasheet(160/243 Pages) STMICROELECTRONICS

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I2C bus interface (I2C)

ST72325xxx-Auto

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Doc ID 13770 Rev 3

16.3

General description

In addition to receiving and transmitting data, this interface converts it from serial to parallel

format and vice versa, using either an interrupt or polled handshake. The interrupts are

enabled or disabled by software. The interface is connected to the I2C bus by a data pin

(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a

fast I2C bus. This selection is made by software.

16.3.1

Mode selection

The interface can operate in the four following modes:

●

Slave transmitter/receiver

●

Master transmitter/receiver

By default, it operates in slave mode.

The interface automatically switches from slave to master after it generates a START

condition and from master to slave in case of arbitration loss or a STOP generation, allowing

then Multimaster capability.

16.3.2

Communication flow

In Master mode, it initiates a data transfer and generates the clock signal. A serial data

transfer always begins with a start condition and ends with a stop condition. Both start and

stop conditions are generated in master mode by software.

In Slave mode, the interface is capable of recognizing its own address (7- or 10-bit), and the

General Call address. The General Call address detection may be enabled or disabled by

software.

Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the

start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is

always transmitted in Master mode.

A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must

send an acknowledge bit to the transmitter. Refer to Figure 68.

Figure 68.

I2C bus protocol

Acknowledge may be enabled and disabled by software.

The I2C interface address and/or general call address can be selected by software.

The speed of the I2C interface may be selected between standard (up to 100 kHz) and fast

I2C (up to 400 kHz).

SCL

SDA

MSB

ACK

STOP

START

CONDITION

VR02119B

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