STM32F410RB datasheet(98/142 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32F410x8/B

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DocID028094 Rev 5

Figure 29. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 58. Otherwise the reset is not taken into account by the device.

6.3.18

TIM timer characteristics

The parameters given in Table 59 are guaranteed by design.

Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 59. TIMx characteristics(1)(2)

1. TIMx is used as a general term to refer to the TIM1 to TIM11 timers.

2. Guaranteed by design.

Symbol

Parameter

Conditions(3)

3. The maximum timer frequency on APB1 is 50 MHz and on APB2 is up to 100 MHz, by setting the TIMPRE

bit in the RCC_DCKCFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = HCKL, otherwise

TIMxCLK >= 4x PCLKx.

Min

Max

Unit

tres(TIM)

Timer resolution time

AHB/APBx

prescaler=1 or 2 or 4,

fTIMxCLK = 100 MHz

tTIMxCLK

11.9

AHB/APBx

prescaler>4, fTIMxCLK =

100 MHz

tTIMxCLK

11.9

fEXT

Timer external clock

frequency on CH1 to

CH4

fTIMxCLK = 100 MHz

0fTIMxCLK/2

MHz

050

MHz

ResTIM

Timer resolution

16/32

bit

tCOUNTER

16-bit counter clock

period when internal

clock is selected

fTIMxCLK = 100 MHz

0.0119

780

µs

tMAX_COUNT

Maximum possible count

with 32-bit counter

65536 ×

65536

tTIMxCLK

fTIMxCLK = 100 MHz

51.1

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