AD5308 datasheet(13/19 Pages) AD

13 / 19 page

REV. B

AD5308/AD5318/AD5328

–13–

VDD

These bits are set when VDD is to be used as reference.

The first group of DACs (A, B, C, and D) can be set

up to use VDD by setting Bit 0, and the second group of

DACs (E, F, G, and H) by setting Bit 1. The VDD bits

have priority over the BUF bits.

When VDD is used as the reference, it will always be

unbuffered and with an output range of 0 V to VREF,

regardless of the state of the GAIN and BUF bits.

LDAC Mode

LDAC mode controls LDAC, which determines when data is

transferred from the input registers to the DAC registers. There

are three options when updating the DAC registers, as shown in

Table III.

LDAC Mode

Bit

Bits

Bit

12 .... 2

Description

x ..... x

LDAC Low

x ..... x

LDAC High

x ..... x

LDAC Single Update

x ..... x

Reserved

LDAC Low (00): This option sets LDAC permanently low,

allowing the DAC registers to be updated continuously.

LDAC High (01): This option sets LDAC permanently high.

The DAC registers are latched, and the input registers may

change without affecting the contents of the DAC registers.

This is the default option for this mode.

LDAC Single Update (10): This option causes a single pulse on

LDAC, updating the DAC registers once.

Reserved (11): Reserved.

Power-Down Mode

The individual channels of the AD5308/AD5318/AD5328 can

be powered down separately. The control mode for this is (10).

On completion of this write sequence, the channels that have

been set to 1 are powered down.

Table II. Control Words for the AD53x8

D/C Control Bits

98765

Mode

(GAIN Bits)(BUF Bits)(VDD Bits)Gain of Output Amplifier

xxxxx

E..H

A..D

E..H

A..D

E..H

A..D

and Reference Selection

(

LDAC Bits)

xxxxxx

1/0

LDAC

(Channels)

xxxH

Power-Down

(RESET)

1/0

xxxxxx

Reset

Reset Mode

This mode consists of two possible reset functions, as outlined

in Table IV.

Table IV. Reset Mode

Bit

11 .... 0

Description

110

x .... x

DAC Data Reset

111

x .... x

Data and Control Reset

DAC Data Reset: On completion of this write sequence, all

DAC registers and input registers are filled with 0s.

Data and Control Reset: This function carries out a DAC data

reset and also resets all the control bits (GAIN, BUF, VDD,

LDAC, and power-down channels) to their power-on conditions.

Low Power Serial Interface

To minimize the power consumption of the device, the interface

powers up fully only when the device is being written to, i.e., on

the falling edge of

SYNC. The SCLK and DIN input buffers

are powered down on the rising edge of

SYNC.

LOAD DAC INPUT (

LDAC) FUNCTION

Access to the DAC registers is controlled by both the

LDAC

pin and the

LDAC mode bits. The operation of the LDAC

function can be likened to the configuration shown in Figure 9.

EXTERNAL

LDAC PIN

INTERNAL

LDAC MODE

LDAC FUNCTION

Figure 9.

LDAC Function

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