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AD5308 Datasheet(PDF) 2 Page - Analog Devices

Part # AD5308
Description  2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
PDF  19 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD5308 Datasheet(HTML) 2 Page - Analog Devices

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REV. B
–2–
AD5308/AD5318/AD5328–SPECIFICATIONS (V
DD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k
to
GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.)
A Version
2
B Version
2
Parameter
1
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5308
Resolution
8
8
Bits
Relative Accuracy
±0.15
±1
±0.15
±0.75 LSB
Differential Nonlinearity
±0.02
±0.25
±0.02
±0.25 LSB
Guaranteed Monotonic by Design over All Codes
AD5318
Resolution
10
10
Bits
Relative Accuracy
±0.5
±4
±0.5
±3
LSB
Differential Nonlinearity
±0.05
±0.50
±0.05
±0.50 LSB
Guaranteed Monotonic by Design over All Codes
AD5328
Resolution
12
12
Bits
Relative Accuracy
±2
±16
±2
±12
LSB
Differential Nonlinearity
±0.2
±1.0
±0.2
±1.0
LSB
Guaranteed Monotonic by Design over All Codes
Offset Error
±5
±60
±5
±60
mV
VDD = 4.5 V, Gain = +2. See Figures 2 and 3.
Gain Error
±0.30
±1.25
±0.30
±1.25 % of FSR
VDD = 4.5 V, Gain = +2. See Figures 2 and 3.
Lower Deadband
5
10
60
10
60
mV
See Figure 2. Lower deadband exists only if offset
error is negative.
Upper Deadband
5
10
60
10
60
mV
See Figure 3. Upper deadband exists only if VREF =
VDD and offset plus gain error is positive.
Offset Error Drift
6
–12
–12
ppm of FSR/
°C
Gain Error Drift
6
–5
–5
ppm of FSR/
°C
DC Power Supply Rejection Ratio
6
–60
–60
dB
VDD =
± 10%
DC Crosstalk
6
200
200
µVR
L = 2 k
Ω to GND or V
DD
DAC REFERENCE INPUTS
6
VREF Input Range
1.0
VDD
1.0
VDD
V
Buffered Reference Mode
0.25
VDD
0.25
VDD
V
Unbuffered Reference Mode
VREF Input Impedance (RDAC)
>10.0
>10.0
M
Ω
Buffered Reference Mode and Power-Down Mode
37.0
45.0
37.0
45.0
k
Ω
Unbuffered Reference Mode. 0 V to VREF
Output Range.
18.0
22.0
18.0
22.0
k
Ω
Unbuffered Reference Mode. 0 V to 2 VREF
Output Range.
Reference Feedthrough
–70.0
–70.0
dB
Frequency = 10 kHz
Channel-to-Channel Isolation
–75.0
–75.0
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
7
0.001
0.001
V
This is a measure of the minimum and maximum
Maximum Output Voltage
7
VDD – 0.001
VDD – 0.001
V
drive capability of the output amplifier.
DC Output Impedance
0.5
0.5
Ω
Short Circuit Current
25.0
25.0
mA
VDD = 5 V
16.0
16.0
mA
VDD = 3 V
Power-Up Time
2.5
2.5
µs
Coming Out of Power-Down Mode. VDD = 5 V.
5.0
5.0
µs
Coming Out of Power-Down Mode. VDD = 3 V.
LOGIC INPUTS
6
Input Current
±1
±1
µA
VIL, Input Low Voltage
0.8
0.8
V
VDD = 5 V
± 10%
0.8
0.8
V
VDD = 3 V
± 10%
0.7
0.7
V
VDD = 2.5 V
VIH, Input High Voltage
1.7
1.7
V
VDD = 2.5 V to 5.5 V; TTL and CMOS
Compatible
Pin Capacitance
3.0
3.0
pF
POWER REQUIREMENTS
VDD
2.5
5.5
2.5
5.5
V
IDD (Normal Mode)
8
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
1.0
1.8
1.0
1.8
mA
All DACs in Unbuffered Mode. In Buffered mode,
VDD = 2.5 V to 3.6 V
0.7
1.5
0.7
1.5
mA
extra current is typically x
µA per DAC; x = (5 µA
+ VREF/RDAC)/4.
IDD (Power-Down Mode)
9
VIH = VDD and VIL = GND
VDD = 4.5 V to 5.5 V
0.4
1
0.4
1
µA
VDD = 2.5 V to 3.6 V
0.12
1
0.12
1
µA
NOTES
1See the Terminology section.
2Temperature range (A, B Version): –40
°C to +105°C; typical at +25°C.
3DC specifications tested with the outputs unloaded unless stated otherwise.
4Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).
5This corresponds to x codes. x = deadband voltage/LSB size.
6Guaranteed by design and characterization; not production tested.
7For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V
REF = VDD and offset plus gain error
must be positive.
8Interface inactive. All DACs active. DAC outputs unloaded.
9All eight DACs powered down.
Specifications subject to change without notice.



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