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AT94S Secure Family

2314D–FPSLI–2/04

Internal Architecture

For details of the AT94S Secure FPSLIC architecture, please refer to the AT94K

FPSLIC datasheet and the AT17 Series Configuration Memory datasheet, available on

the Atmel web site at http://www.atmel.com. This document only describes the differ-

ences between the AT94S Secure FPSLIC and the AT94K FPSLIC.

FPSLIC and

Configurator

Interface

•

Fully In-System Programmable and Re-programmable

•

When Security Bit Set:

–

Data Verification Disabled

–

Data Transfer to FPSLIC not Externally Visible

–

Secured EEPROM Will Only Boot the FPSLIC Device or Respond to a Chip

Erase

•

When Security Bit Cleared:

–

Entire Chip Erase Performed

–

In-System Programming Enabled

–

Data Verification Enabled

External Data pins allow for In-System Programming of the device and setting of the

EEPROM-based security bit. When the security bit is set (active) this programming con-

nection will only respond to a device erase command. Data cannot be read out of the

external programming/data pins when the security bit is set. The part can be re-pro-

grammed, but only after first being erased.

Programming and

Configuration Timing

Characteristics

Atmel’s Configurator Programming Software (CPS), available from the Atmel web site

(http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3191), creates the pro-

gramming algorithm for the embedded configurator; however, if you are planning to

write your own software or use other means to program the embedded configurator, the

section below includes the algorithm and other details.

The FPSLIC Configurator The FPSLIC Configurator is a serial EEPROM memory which is used to load program-

mable devices. This document describes the features needed to program the

Configurator from within its programming mode (i.e., when SER_EN is driven Low).

Reference schematics are supplied for ISP applications.

Serial Bus Overview

The serial bus is a two-wire bus; one wire (cSCK) functions as a clock and is provided

by the programmer, the second wire (cSDA) is a bi-directional signal and is used to pro-

vide data and control information.

Information is transmitted on the serial bus in messages. Each MESSAGE is preceded

by a Start Condition and ends with a Stop Condition. The message consists of an inte-

ger number of bytes, each byte consisting of 8 bits of data, followed by a ninth

Acknowledge Bit. This Acknowledge Bit is provided by the recipient of the transmitted

byte. This is possible because devices may only drive the cSDA line Low. The system

must provide a small pull-up current (1 k

Ω equivalent) for the cSDA line.

The MESSAGE FORMAT for read and write instructions consists of the bytes shown in

“Bit Format” on page 5.

While writing, the programmer is responsible for issuing the instruction and data. While

reading, the programmer issues the instruction and acknowledges the data from the

Configurator as necessary.

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