5

CAT25010/20/40

Doc. No. 1006, Rev. L

Status Register Bits

Array Address

Protection

BP1

BP0

Protected

0

0

None

No Protection

0

1

25010: 60-7F

Quarter Array Protection

25020: C0-FF

25040: 180-1FF

1

0

25010: 40-7F

Half Array Protection

25020: 80-FF

25040: 100-1FF

1

1

25010: 00-7F

Full Array Protection

25020: 00-FF

25040: 000-1FF

BLOCK PROTECTION BITS

76543210

1111

BP1

BP0

WEL

RDY

STATUS REGISTER

clock for SPI modes (0,0 & 1,1).

SCK: Serial Clock

SCK is the serial clock pin. This pin is used to synchronize

the communication between the microcontroller and the

CAT25010/20/40. Opcodes, byte addresses, or data

present on the SI pin are latched on the rising edge of the

SCK. Data on the SO pin is updated on the falling edge

of the SCK for SPI modes (0,0 & 1,1) .

CS

CS

CS

CS

CS: Chip Select

CS is the Chip select pin. CS low enables the CAT25010/

20/40 and

CS high disables the CAT25010/20/40. CS

high takes the SO output pin to high impedance and

forces the devices into a Standby Mode (unless an

internal write operation is underway) The CAT25010/

20/40 draws ZERO current in the Standby mode. A high

to low transition on

CS is required prior to any sequence

being initiated. A low to high transition on

CS after a valid

write sequence is what initiates an internal write cycle.

WP

WP

WP

WP

WP: Write Protect

WP is the Write Protect pin. The Write Protect pin will

allow normal read/write operations when held high.

When

WP is tied low all write operations are inhibited.

WP held low while CS is low will interrupt a write to the

CAT25010/20/40. If the internal write cycle has already

been initiated,

WP going low will have no effect on any

write operation. Figure 10 illustrates the

WP timing

sequence during a write operation.

HOLD

HOLD

HOLD

HOLD

HOLD: Hold

The

HOLD pin is used to pause transmission to the

CAT25010/20/40 while in the middle of a serial sequence

without having to re-transmit entire sequence at a later

time. To pause,

HOLD must be brought low while SCK

is low. The SO pin is in a high impedance state during

the time the part is paused, and transitions on the SI pins

will be ignored. To resume communication,

HOLD is

brought high, while SCK is low. (

HOLD should be held

high any time this function is not being used.)

HOLD may

resistor. Figure 9 illustrates hold timing sequence.