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LM96000 Datasheet(PDF) 2 Page - National Semiconductor (TI) |
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LM96000 Datasheet(HTML) 2 Page - National Semiconductor (TI) |
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2 / 28 page  Connection Diagram 24 Pin TSSOP 20084602 NS Package MTC24E Top View LM96000CIMT (61 units per rail), or LM96000CIMTX (2500 units per tape and reel) Pin Descriptions Symbol Pin Type Name and Function/Connection SMBDAT 1 Digital I/O (Open-Drain) System Management Bus Data. Open-drain output. 5V tolerant, SMBus 2.0 compliant. SMBCLK 2 Digital Input System Management Bus Clock. Tied to Open-drain output. 5V tolerant, SMBus 2.0 compliant. VID0 5 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID1 6 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID2 7 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID3 8 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. VID4 19 Digital Input Voltage identification signal from the processor. This value is read in the VID0–VID4 Status Register. 3.3V 4 POWER +3.3V pin. Can be powered by +3.3V Standby power if monitoring in low power states is required. This pin also serves as the analog input to monitor the 3.3V supply. This pin should be bypassed with a 0.1µf capacitor in parallel with 100pf. A bulk capacitance of approximately 10µf needs to be in the near vicinity of the LM96000. GND 3 GROUND Ground for all analog and digital circuitry. 5V 20 Analog Input Analog input for +5V monitoring. 12V 21 Analog Input Analog input for +12V monitoring. 2.5V 22 Analog Input Analog input for +2.5V monitoring. VCCP_IN 23 Analog Input Analog input for VCCP (processor voltage) monitoring. www.national.com 2 |
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