AS8C403625 datasheet(7/19 Pages) ALSC

7 / 19 page

AS8C403625, AS8C401825, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect

Commercial Temperature Range

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (1)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Figure 2. Lumped Capacitive Load, Typical Derating

Figure 1. AC Test Load

AC Test Load

AC Test Conditions

(VDDQ = 3.3V)

NOTE:

1. The

LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ in will be internally pulled to VSS if they are not actively driven in the application.

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while

ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

VDDQ/2

50Ω

I/O

Z0 =50Ω

5280 drw 03

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

|ILI|

Input Leakage Current

VDD = Max., VIN = 0V to VDD

___

5µ A

|ILI|

ZZ ,

LBO and JTAG Input Leakage Current(1)

VDD = Max., VIN = 0V to VDD

___

µ A

|ILO|

Output Leakage Current

VOUT = 0V to VDDQ, Device Deselected

___

5µ A

VOL

Output Low Voltage

IOL = +8mA, VDD = Min.

___

0.4

VOH

Output High Voltage

IOH = -8mA, VDD = Min.

2.4

___

5280 tbl 08

Symbol

Parameter

Test Conditions

7.5ns

8ns

8.5ns

Unit

Com'l Only

Com'l

Ind

Com'l

Ind

IDD

Operating Power Supply Current

Device Se lected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)

255

200

210

180

190

ISB1

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)

ISB2

Clock Running Power

Supply Current

Device Deselected, Outputs Open, VDD = Max.,

VDDQ = Max., VIN > VHD or < VLD, f = fMAX (2,.3)

IZZ

Full Sleep Mode Supply Current

ZZ > VHD, VDD = Max.

5280 tbl 09

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

0 to 3V

2ns

1.5V

See Figure 1

5280 tbl 10

20 30 50

100

200

∆tCD

(Typical, ns)

Capacitance (pF)

5280 drw 05

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