COP880C datasheet(17/31 Pages) NSC

17 / 31 page

Functional Description (Continued)

time into the timer, which continues to run. By alternately

loading in the on time and the off time at each successive

interrupt a PWM frequency can be easily generated.

Control Registers

CNTRL REGISTER (ADDRESS X’00EE)

The Timer and MICROWIRE/PLUS control register contains

the following bits:

SL1 & SL0 Select the MICROWIRE/PLUS clock divide-by

IEDG

External interrupt edge polarity select

(0 = rising edge, 1 = falling edge)

MSEL

Enable MICROWIRE/PLUS functions SO and

TRUN

Start/Stop the Timer/Counter (1 = run, 0 = stop)

TC3

Timer input edge polarity select (0 = rising

edge, 1 = falling edge)

TC2

Selects the capture mode

TC1

Selects the timer mode

TC1

TC2

TC3

TRUN

MSEL

IEDG

SL1

SL0

BIT

PSW REGISTER (ADDRESS X’00EF)

The PSW register contains the following select bits:

GIE

Global interrupt enable

ENI

External interrupt enable

BUSY MICROWIRE/PLUS busy shifting

IPND

External interrupt pending

ENTI

Timer interrupt enable

TPND Timer interrupt pending

Carry Flag

Half carry Flag

TPND

ENTI

IPND

BUSY

ENI

GIE

BIT

Addressing Modes

This is the “normal” mode of addressing. The operand is the

memory addressed by the B register or X register.

DIRECT

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

IMMEDIATE

The instruction contains an 8-bit immediate field as the

operand.

(AUTO INCREMENT AND DECREMENT)

This is a register indirect mode that automatically increments

or decrements the B or X register after executing the instruc-

tion.

RELATIVE

This mode is used for the JP instruction, the instruction field

is added to the program counter to get the new program

location. JP has a range of from −31 to +32 to allow a one

byte relative jump (JP + 1 is implemented by a NOP instruc-

tion). There are no “pages” when using JP, all 15 bits of PC

are used.

Memory Map

All RAM, ports and registers (except A and PC) are mapped

into data memory address space.

Address

Contents

00 to 6F

On Chip RAM Bytes

70 to 7F

Unused RAM Address Space (Reads as all Ones)

80 to BF

Expansion Space for future use

C0 to

Expansion Space for I/O and Registers

D0 to

On Chip I/O and Registers

Port L Data Register

Port L Configuration Register

Port L Input Pins (Read Only)

Reserved for Port L

Port G Data Register

Port G Configuration Register

Port G Input Pins (Read Only)

Port I Input Pins (Read Only)

Port C Data Register

Port C Configuration Register

Port C Input Pins (Read Only)

Reserved for Port C

Port D Data Register

DD–DF

Reserved for Port D

E0 to EF

On Chip Functions and Registers

E0–E7

Reserved for Future Parts

Reserved

MICROWIRE/PLUS Shift Register

Timer Lower Byte

Timer Upper Byte

Timer Autoload Register Lower Byte

Timer Autoload Register Upper Byte

CNTRL Control Register

PSW Register

F0 to FF

On Chip RAM Mapped as Registers

X Register

SP Register

DS010802-13

FIGURE 11. Timer Application

COP880C Datasheet(PDF) 17 Page - National Semiconductor (TI)

COP880C Datasheet(HTML) 17 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Datasheet Download

Link URL