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HD404848FS Datasheet(PDF) 41 Page - Hitachi Semiconductor |
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HD404848FS Datasheet(HTML) 41 Page - Hitachi Semiconductor |
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41 / 125 page ![]() HD404849 Series 41 Bit Initial value Read/Write Bit name 3 0 W SSR3* 2 0 W SSR2 0 — — Not used 1 0 W SSR1 System clock select register (SSR: $029) SSR1 0 1 SSR2 0 1 ratio selection fSUB = fX/8 fSUB = fX/4 SSR3 0 1 32-kHz oscillation stop Oscillation operates in stop mode Oscillation stops in stop mode 32-kHz oscillation division System oscillation frequency selection 0.4 MHz – 1.0 MHz 1.6 MHz – 4.5 MHz Note: * SSR3 is cleared only by a RESET input. SSR3 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR3 will also not be cleared upon entering stop mode. Figure 26 System Clock Select Register |
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