R5F117BC datasheet(13/102 Pages) RENESAS

13 / 102 page

RL78/I1D

1. OUTLINE

R01DS0244EJ0220 Rev. 2.20

Page 13 of 99

Feb 20, 2017

1.6

Outline of Functions

Remark

This outline describes the functions at the time when Peripheral I/O redirection register 0 (PIOR0) are set

to 00H.

Note

The flash library uses RAM in self-programming and rewriting of the data flash memory.

The target products and start address of the RAM areas used by the flash library are shown below.

R5F117xC (x = A, B, G): Start address FF300H

For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for RL78 Family

(R20UT2944)

(1/2)

Item

20-pin

24-pin

30-pin

32-pin

48-pin

R5F1176x

(x = 8, A)

R5F1177x

(x = 8, A)

R5F117Ax

(x = 8, A, C)

R5F117Bx

(x = A, C)

R5F117Gx

(x = A, C)

Code flash memory (KB)

8 to 16 KB

8 to 32 KB

16 to 32 KB

Data flash memory (KB)

2 KB

RAM

0.7 to 2.0 KB

0.7 to 3.0 KB Note

2.0 to 3.0 KB Note

Address space

1 MB

Main system

clock

High-speed system clock (fMX)

X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)

HS (High-speed main) mode:1 to 20 MHz (VDD = 2.7 to 3.6 V),

HS (High-speed main) mode:1 to 16 MHz (VDD = 2.4 to 3.6 V),

LS (Low-speed main) mode:1 to 8 MHz (VDD = 1.8 to 3.6 V),

LV (Low-voltage main) mode:1 to 4 MHz (VDD = 1.6 to 3.6 V),

LP (Low-power main) mode:1 MHz (VDD = 1.8 to 3.6 V)

High-speed on-chip oscillator

clock (fIH) Max: 24 MHz

HS (High-speed main) mode: 1 to 24 MHz (VDD = 2.7 to 3.6 V),

HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 3.6 V),

LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 3.6 V),

LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 3.6 V),

LP (Low-power main) mode: 1 MHz (VDD = 1.8 to 3.6 V)

Middle-speed on-chip oscillator

clock (fIM) Max: 4 MHz

Subsystem

clock

Subsystem clock oscillator

(fSX, fSXR)

—

XT1 (crystal) oscillation

32.768 kHz (TYP.): VDD = 1.6 to 3.6 V

Low-speed on-chip oscillator

clock (fIL)

15 kHz (TYP.): VDD = 1.6 to 3.6 V

General-purpose register

8 bits

× 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time

0.04167

μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)

0.05

μs (High-speed system clock: fMX = 20 MHz operation)

—30.5

μs

(Subsystem clock oscillator clock: fSX = 32.768 kHz

operation)

Instruction set

• Data transfer (8/16 bits)

• Adder and subtractor/logical operation (8/16 bits)

• Multiplication (8 bits

× 8 bits, 16 bits × 16 bits), Division (16 bits ÷ 16 bits, 32 bits ÷ 32 bits)

• Multiplication and Accumulation (16 bits

× 16 bits + 32 bits)

• Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.

I/O port

Total

CMOS I/O

1519

2133

CMOS input

33555

N-ch open-drain I/O

(6 V tolerance)

————

Timer

16-bit timer

4 channels

Watchdog timer

1 channel

Real-time clock

1 channel

12-bit interval timer

1 channel

8/16-bit interval timer

4 channels (8 bit) / 2 channels (16 bit)

Timer output

24344

RTC output

—

1 channel

•1 Hz

(subsystem clock generator and RTC/other clock:

fSX = 32.768 kHz)

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