R5F11EBAA datasheet(39/70 Pages) RENESAS

39 / 70 page

RL78/G1G

2. ELECTRICAL SPECIFICATIONS

R01DS0241EJ0130 Rev. 1.30

Page 39 of 67

Sep 30, 2016

Note 1.

Transfer rate in the SNOOZE mode is 4800 bps only.

However, the SNOOZE mode cannot be used when FRQSEL4 = 1.

Note 2.

Use it with VDD

 Vb.

Note 3.

The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:

HS (high-speed main) mode:

24 MHz (2.7 V

 VDD  5.5 V)

LS (low-speed main) mode:

8 MHz (2.7 V

 VDD  5.5 V)

Caution

Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq

pin by using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL, see the

DC characteristics with TTL input buffer selected.

Remark 1.

Vb[V]: Communication line voltage

Remark 2.

q: UART number (q = 0, 1), g: PIM and POM number (g = 0, 5)

Remark 3.

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00 to 03)

Remark 4.

VIH and VIL below are observation points for the AC characteristics of the serial array unit when communicating at

different potentials in UART mode.

4.0 V

 VDD  5.5 V, 2.7 V  Vb  4.0 V: VIH = 2.2 V, VIL = 0.8 V

2.7 V

 VDD < 4.0 V, 2.3 V  Vb  2.7 V: VIH = 2.0 V, VIL = 0.5 V

2.7 V

 VDD < 3.3 V, 1.6 V  Vb  2.0 V: VIH = 1.50 V, VIL = 0.32 V

(6)

Communication at different potential (2.5 V, 3 V) (UART mode)

(TA = -40 to +85

C, 2.7 V  VDD  5.5 V, VSS = 0 V)

(1/2)

Parameter

Symbol

Conditions

HS (high-speed main) mode

LS (low-speed main) mode

Unit

MIN.

MAX.

MIN.

MAX.

Transfer rate

Reception

4.0 V

 VDD  5.5 V,

2.7 V

 Vb  4.0 V

fMCK/6 Note 1

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLK Note 3

4.0

1.3

Mbps

2.7 V

 VDD < 4.0 V,

2.3 V

 Vb  2.7 V

fMCK/6 Note 1

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLK Note 3

4.0

1.3

Mbps

2.7 V

 VDD < 3.3 V,

1.6 V

 Vb  2.0 V

fMCK/6

Notes 1, 2

fMCK/6

Notes 1, 2

bps

Theoretical value of the maximum

transfer rate

fMCK = fCLK Note 3

4.0

1.3

Mbps

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