R5F100GC datasheet(156/202 Pages) RENESAS

156 / 202 page

RL78/G13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105

C)

Page 156 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock

output) (1/3)

(TA =

40 to +105C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

HS (high-speed main) Mode

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

4.0 V

 EVDD0  5.5 V, 2.7 V  Vb  4.0

Cb = 30 pF, Rb = 1.4 k



600

2.7 V

 EVDD0 < 4.0 V, 2.3 V  Vb  2.7

Cb = 30 pF, Rb = 2.7 k



1000

SCKp cycle time

tKCY1

 4/fCLK

2.4 V

 EVDD0 < 3.3 V, 1.6 V  Vb  2.0

Cb = 30 pF, Rb = 5.5 k



2300

4.0 V

 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k



tKCY1/2

 150

2.7 V

 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k



tKCY1/2

 340

SCKp high-level width tKH1

2.4 V

 EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,

Cb = 30 pF, Rb = 5.5 k



tKCY1/2

 916

4.0 V

 EVDD0  5.5 V, 2.7 V  Vb  4.0 V,

Cb = 30 pF, Rb = 1.4 k



tKCY1/2

 24

2.7 V

 EVDD0 < 4.0 V, 2.3 V  Vb  2.7 V,

Cb = 30 pF, Rb = 2.7 k



tKCY1/2

 36

SCKp low-level width

tKL1

2.4 V

 EVDD0 < 3.3 V, 1.6 V  Vb  2.0 V,

Cb = 30 pF, Rb = 5.5 k



tKCY1/2

 100

Caution

Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the

20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and

SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For

VIH and VIL, see the DC characteristics with TTL input buffer selected.

(Remarks are listed two pages after the next page.)

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