R5F100GD datasheet(166/202 Pages) RENESAS

166 / 202 page

RL78/G13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105

C)

Page 166 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

Simplified I

2C mode connection diagram (during communication at different potential)

SDAr

SCLr

SDA

SCL

User device

RL78

microcontroller

Simplified I

2C mode serial transfer timing (during communication at different potential)

SDAr

tLOW

tHIGH

tHD:DAT

SCLr

tSU:DAT

1/fSCL

Caution

Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the N-ch

open drain output (VDD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-

pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output

mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.

Remarks 1. Rb[

]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)

load capacitance, Vb[V]: Communication line voltage

2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)

fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,

n: Channel number (mn = 00, 01, 02, 10, 12, 13)

R5F100GD Datasheet(PDF) 166 Page - Renesas Technology Corp