R5F100GD datasheet(31/202 Pages) RENESAS

31 / 202 page

RL78/G13

1. OUTLINE

Page 31 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

 100-pin plastic LQFP (14 × 20 mm, 0.65 mm pitch)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

RL78/G13

(Top View)

1 2 3

4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

100

P146/(INTP4)

P111/(INTP11)

P110/(INTP10)

P101

P10/SCK00/SCL00/(TI07)/(TO07)

P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)

P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)

P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)

P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)

P15/SCK20/SCL20/(TI02)/(TO02)

P16/TI01/TO01/INTP5/(SI00)/(RXD0)

P17/TI02/TO02/(SO00)/(TXD0)

P57/(INTP3)

P56/(INTP1)

P55/(PCLBUZ1)/(SCK00)

P54/SCK31/SCL31

P53/SI31/SDA31

P52/SO31

P51/SO11

P50/SI11/SDA11

P120/ANI19

P47/INTP2

P46/INTP1/TI05/TO05

P45/SO01

P44/SI01/SDA01

P43/SCK01/SCL01

P42/TI04/TO04

P41

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

VSS

EVSS0

VDD

EVDD0

Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.

2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).

3. Connect the REGC pin to Vss via a capacitor (0.47 to 1

F).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2. When using the microcontroller for an application where the noise generated inside the

microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0

and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.

3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O

redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register

(PIOR) in the RL78/G13 User’s Manual.

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