S3A7 datasheet(59/133 Pages) RENESAS

59 / 133 page

R01DS0263EU0100 Rev.1.00

Page 59 of 130

Feb 23, 2016

S3A7

2. Electrical Characteristics

Figure 2.30

PLL clock oscillation start timing (PLL is operated after main clock oscillation has settled)

Figure 2.31

Sub-clock oscillation start timing

2.3.3

Reset Timing

Note 1.

When OFS1.LVDAS = 0.

Note 2.

When OFS1.LVDAS = 1.

Note 3.

When IWDTCR.CKS[3:0] = 0000b.

Table 2.23

Reset timing

Item

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

At power-on

tRESWP

Figure 2.32

Other than above

tRESW

μs

Figure 2.33

Wait time after RES cancellation

(at power-on)

LVD0: enable*1

tRESWT

0.7

-ms

Figure 2.32

LVD0: disable*2

0.3

Wait time after RES cancellation

(during powered-on state)

LVD0: enable*1

tRESWT2

0.5

μs

Figure 2.33

LVD0: disable*2

0.05

Reset period

IWDT*3

tRESWIW

-IWDT

clock

cycle

Figure 2.34

Internal reset

(except IWDT)

tRESWIR

-ICLK

cycle

Wait time after Internal reset cancellation

LVD0: enable*1

tRESWT3

0.5

μs

LVD0: disable*2

0.05

PLLCCR2.PLLEN

PLL clock

MOSCCR.MOSTP

tMAINOSC

Main clock oscillator output

tPLL

Sub-clock oscillator output

SOSCCR.SOSTP

tSUBOSC

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