S3A7 datasheet(2/133 Pages) RENESAS

2 / 133 page

R01DS0263EU0100 Rev.1.00

Page 2 of 130

Feb 23, 2016

S3A7

1. Overview

Overview

The S3A7 MCU comprises multiple series of software- and pin-compatible ARM-based 32-bit MCUs that share a

common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

This MCU provides an optimal combination of low-power, high-performance ARM® Cortex®-M4 core running up to 48

MHz with the following features:

 Up to 1-MB code flash memory

 192-KB SRAM

 Segment LCD Controller (SLCDC)

 Capacitive Touch Sensing Unit (CTSU)

 USB 2.0 Full-Speed Module (USBFS)

 14-bit ADC

 12-bit DAC

 Security features.

1.1

Function Outline

Table 1.1

ARM core

Feature

Functional description

ARM Cortex-M4

 Maximum operating frequency: up to 48 MHz

 ARM Cortex-M4:

- Revision: r0p1-01rel0

- ARMv7E-M architecture profile

- Single Precision Floating Point Unit compliant with the ANSI/IEEE Std 754-2008

 ARM Memory Protection Unit (MPU):

- ARMv7 Protected Memory System Architecture

- 8 protect regions

 SysTick timer:

- Driven by LOCO clock

Table 1.2

Memory

Feature

Functional description

Code flash memory

Maximum 1 MB code flash memory. See section 48, Flash Memory in User's Manual.

Data flash memory

16 KB data flash memory. See section 48, Flash Memory in User's Manual.

Option-Setting Memory

The Option-Setting Memory determines the state of the MCU after a reset.

See section 7, Option-Setting Memory in User's Manual.

Memory Mirror Function (MMF)

The MMF can be configured to mirror the desired application image load address in code flash

memory to the application image link address in the unused memory 23-bit space (memory

mirror space addresses). The user application code is developed and linked to run from this

MMF destination address. The user application code does not need to know the load location

where it is stored in code flash memory. See section 5, Memory Mirror Function (MMF) in

User's Manual.

SRAM

This MCU has an on-chip high-speed SRAM with either parity-bit or Error Correction Code

(ECC). There is an area in SRAM0 that provides error correction capability using ECC. See

section 47, SRAM in User's Manual.

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