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WM8533 Datasheet(PDF) 9 Page - Cirrus Logic |
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WM8533 Datasheet(HTML) 9 Page - Cirrus Logic |
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9 / 41 page ![]() Production Data WM8533 w PD, July 2012, Rev 4.0 9 AUDIO INTERFACE TIMING – MASTER MODE Figure 2 Master Mode Digital Audio Data Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Input Timing Information LRCLK propagation delay from BCLK falling edge tDL 4 16 ns DACDAT setup time to BCLK rising edge tDST 22 ns DACDAT hold time from BCLK rising edge tDHT 25 ns Table 1 Master Mode Audio Interface Timing |
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