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WM7236 Datasheet(PDF) 7 Page - Cirrus Logic

Part # WM7236
Description  Low Power Bottom Port Digital Silicon Microphone
PDF  14 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM7236 Datasheet(HTML) 7 Page - Cirrus Logic

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WM7236E
Rev 4.0
7
TERMINOLOGY
1.
Sensitivity (dBFS)
– Sensitivity is a measure of the microphone output response to the acoustic pressure of a 1kHz 94dB SPL
(1Pa RMS) sine wave. This is referenced to the output Full Scale Range (FSR) of the microphone.
2.
Full Scale Range (FSR)
– Sensitivity, Electrical Noise Floor and Power Supply Rejection are measured with reference to the
output Full Scale Range (FSR) of the microphone. FSR is defined as the amplitude of a 1kHz sine wave output whose positive
peak value reaches 100% density of logic 1s and whose negative peak value reaches 0% density of logic 1s. This is the largest
1kHz sine wave that will fit in the digital output range without clipping. Note that, because the definition of FSR is based on a
sine wave, it is possible to support a square wave test signal output whose level is +3dBFS.
3.
Total Harmonic Distortion (%)
– THD is the ratio of the RMS sum of the harmonic distortion products in the specified bandwidth
(see note below) relative to the RMS amplitude of the fundamental (ie. test frequency) output.
4.
Signal-to-Noise Ratio (dB)
– SNR is a measure of the difference in level between the output response of a 1kHz 94dB SPL
sine wave and the idle noise output.
5.
Dynamic Range (dB)
– DR is the ratio of the 1% THD microphone output level (in response to a sine wave input) and the idle
noise output level.
6.
All performance measurements are carried out within a 20Hz to 20kHz bandwidth and, where noted, an A-weighted filter.
Failure to use these filters will result in higher THD and lower SNR values than are found in the Acoustic and Electrical
Characteristics. The brick wall filter removes out-of-band noise.
7.
Hi-Fi Record mode and Voice mode are selected according to CLK frequency, as described above.
8.
Sleep Mode is enabled when the CLK input is stopped; this is a power-saving mode. Normal operation resumes automatically
when the CLK input frequency is within the specified operational limits. Note that the VDD supply is still required in Sleep
mode.



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